> -----Original Message-----
> From: Manna, Animesh <[email protected]>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: [email protected]; [email protected]
> Cc: Shankar, Uma <[email protected]>; Dibin Moolakadan Subrahmanian
> <[email protected]>; [email protected];
> Nikula, Jani <[email protected]>; Manna, Animesh
> <[email protected]>
> Subject: [PATCH v8 16/20] drm/i915/cmtg: Add CMTG HWGB programming
>
> From: Dibin Moolakadan Subrahmanian
> <[email protected]>
>
> Program CMTG guardband to generate the Lower/Upper and early entry
> guardband indicators to the DMC for DC3co control.
>
> Bspec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <[email protected]>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 8 +++++
> 3 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index fb57fa41f721..cc36784e5253 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -400,3 +400,34 @@ void intel_cmtg_disable_interrupt(const struct
> intel_crtc_state *crtc_state)
> intel_cmtg_mask_interrupt(crtc_state, true);
> spin_unlock_irq(&display->irq.lock);
> }
> +
> +#define DC3CO_ENTRY_LATENCY 55
> +#define DC3CO_EXIT_LATENCY 40
Add the bspec reference for this. Also indicate what unit this latency is in.
> +void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 breakeven_gb;
> + u32 dc5_exit_latency;
> + u32 line_time_us = 75;
>From where this 75 come from, add a comment.
> + u32 val;
> +
> + if (!intel_cmtg_is_allowed(crtc_state))
> + return;
> +
> + if (crtc_state->linetime)
> + line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8);
> +
> + /* Break Even Guardband - DC3co Entry Latency / linetime */
> + breakeven_gb = DIV_ROUND_UP(DC3CO_ENTRY_LATENCY,
> line_time_us);
> +
> + /* DC5 Exit Latency - DC3co Exit Latency / linetime */
> + dc5_exit_latency = DIV_ROUND_UP(DC3CO_EXIT_LATENCY,
> line_time_us);
> +
> + val = REG_FIELD_PREP(CMTG_HW_GB_BREAKEVEN_MASK,
> breakeven_gb) |
> + REG_FIELD_PREP(CMTG_HW_GB_DC5_EXIT_LATENCY_MASK,
> dc5_exit_latency) |
> + REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1);
> +
> + intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val);
Should it be cpu_transcoder or cmtg_transcoder ?
With above fixed, this is
Reviewed-by: Uma Shankar <[email protected]>
}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 8fcb44d6398f..2c801a74acf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -23,5 +23,6 @@ void intel_cmtg_sanitize(struct intel_display *display);
> bool
> intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state); void
> intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state); void
> intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 240a02cd4a3a..a4a2a2fe6b66 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -24,4 +24,12 @@
> #define CMTG_SYNC_TO_PORT REG_BIT(29)
> #define CMTG_STATE REG_BIT(23)
>
> +#define _CMTG_HW_GB_A 0x6fa8c
> +#define _CMTG_HW_GB_B 0x6fb8c
> +#define CMTG_HW_GB(trans) _MMIO_TRANS((trans), \
> + _CMTG_HW_GB_A,
> _CMTG_HW_GB_B)
> +#define CMTG_HW_GB_BREAKEVEN_MASK REG_GENMASK(11, 0)
> +#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK REG_GENMASK(27, 16)
> +#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK
> REG_GENMASK(31, 28)
> +
> #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0
