> -----Original Message-----
> From: Manna, Animesh <[email protected]>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: [email protected]; [email protected]
> Cc: Shankar, Uma <[email protected]>; Dibin Moolakadan Subrahmanian
> <[email protected]>; [email protected];
> Nikula, Jani <[email protected]>; Manna, Animesh
> <[email protected]>
> Subject: [PATCH v8 10/20] drm/i915/cmtg: Program VRR control register for
> CMTG transcoder
>
> Add intel_cmtg_set_vrr_ctl() to program TRANS_VRR_CTL for the CMTG
> transcoder. Purposefully avoid using the existing VRR enable path, as many of
> its
> operations are not needed for CMTG.
>
> v2: Use sw state instead of reading from hardware. [Jani]
> v3: Program cmtg vrr control register along with vrr transcoder registers.
> [R-b
> from Uma]
> v4: Split out from vrr timing registers programming.
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Bspec: 68989
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
> 3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 4c8187ddef1f..12f6ef4de0e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -17,6 +17,7 @@
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_vrr.h"
> +#include "intel_vrr_regs.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG) @@ -255,3 +256,22 @@
> void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>
> intel_vrr_set_fixed_rr_timings(crtc_state, cmtg_transcoder); }
> +
> +void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state-
> >cpu_transcoder);
> + u32 vrr_ctl;
> +
> + if (!intel_cmtg_is_allowed(crtc_state))
> + return;
> +
> + vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
> + XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state-
> >vrr.guardband);
> +
> + /* TODO: The code below may need to be revisited once CMRR is
> enabled */
> + if (crtc_state->cmrr.enable)
> + vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> +
> + intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder),
> +vrr_ctl); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 899a2744514c..c92e3a62ff0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -12,6 +12,7 @@ struct intel_display;
> struct intel_crtc_state;
>
> void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool
> lrr);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void
> intel_cmtg_sanitize(struct intel_display *display); diff --git
> a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 2295f6545981..d4a2645cd380 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -932,6 +932,8 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
> vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>
> intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl);
> +
> + intel_cmtg_set_vrr_ctl(crtc_state);
> }
>
> static void intel_vrr_tg_disable(const struct intel_crtc_state
> *old_crtc_state)
> --
> 2.29.0
