Add intel_psr2_in_deep_sleep() to check whether PSR2 is currently in DEEP_SLEEP state. Will be used in subsequent patches.
Signed-off-by: Dibin Moolakadan Subrahmanian <[email protected]> --- drivers/gpu/drm/i915/display/intel_psr.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 1 + 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b7344f2b865e..932aff386023 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2219,6 +2219,27 @@ static void intel_psr_exit(struct intel_dp *intel_dp) intel_dp->psr.active = false; } +bool intel_psr2_in_deep_sleep(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + enum transcoder cpu_transcoder; + bool in_deep_sleep = false; + u32 val; + + mutex_lock(&intel_dp->psr.lock); + + if (!intel_dp->psr.enabled || !intel_dp->psr.sel_update_enabled) + goto out; + + cpu_transcoder = intel_dp->psr.transcoder; + val = intel_de_read(display, EDP_PSR2_STATUS(display, cpu_transcoder)); + in_deep_sleep = (val & EDP_PSR2_STATUS_STATE_MASK) == + EDP_PSR2_STATUS_STATE_DEEP_SLEEP; +out: + mutex_unlock(&intel_dp->psr.lock); + return in_deep_sleep; +} + static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 29723e63888f..d545fdaa0de7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -87,5 +87,6 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp, int intel_psr_min_guardband(struct intel_crtc_state *crtc_state); bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state); bool intel_psr_pr_async_video_timing_supported(struct intel_dp *intel_dp); +bool intel_psr2_in_deep_sleep(struct intel_dp *intel_dp); #endif /* __INTEL_PSR_H__ */ -- 2.43.0
