On 01-06-2026 11:00, Manna, Animesh wrote:
-----Original Message-----
From: Dibin Moolakadan Subrahmanian
<[email protected]>
Sent: Wednesday, May 27, 2026 12:48 AM
To: [email protected]; [email protected]
Cc: Manna, Animesh <[email protected]>; Shankar, Uma
<[email protected]>
Subject: [PATCH v4 03/13] drm/i915/display: Use FIELD_PREP() for DC state
enable bits
Replace open-coded shifts with REG_GENMASK() and REG_FIELD_PREP() for
the DC state enable field.
Suggested-by: Jani Nikula <[email protected]>
Signed-off-by: Dibin Moolakadan Subrahmanian
<[email protected]>
Reviewed-by: Uma Shankar <[email protected]>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 680e7dfdcf1b..efd1a3e56f76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3073,11 +3073,12 @@ enum skl_power_gate {
#define DC_STATE_DC3CO_STATUS REG_BIT(29)
#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
#define HOLD_PHY_PG1_LATCH REG_BIT(20)
-#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
-#define DC_STATE_EN_UPTO_DC6 (2 << 0)
-#define DC_STATE_EN_UPTO_DC3CO (3 << 0)
-#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
+#define DC_STATE_EN_UPTO_DC5_DC6_MASK REG_GENMASK(1, 0)
+#define DC_STATE_EN_DISABLE
REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 0)
+#define DC_STATE_EN_UPTO_DC5
REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 1)
+#define DC_STATE_EN_UPTO_DC6
REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 2)
+#define DC_STATE_EN_UPTO_DC3CO
REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 3)
Misaligned, need extra tab.
Thanks, I'll fix the alignment in the next revision.
Regards,
Animesh
#define DC_STATE_DEBUG _MMIO(0x45520)
#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
--
2.43.0
