This patch set contains fixes for Selective Fetch Early Transport configuration:
- add necessary DSC Early Transport configuration
- corner case fix for Selective Update area when Early Transport is
in use and cursor plane is included into SU are due to alignment.
v2:
- optimize elignment loop
- move register definitions to intel_vdsc_regs.h
- replace patches 3 and 4 with new patches
- drop patch 5
Jouni Högander (4):
drm/i915/psr: Repeat Selective Update area alignment
drm/i915/dsc: Add Selective Update register definitions
drm/i915/dsc: Add helper for writing DSC Selective Update ET
parameters
drm/i915/psr: Write DSC parameters on Selective Update in ET mode
drivers/gpu/drm/i915/display/intel_psr.c | 61 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 +++++++
drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +
.../gpu/drm/i915/display/intel_vdsc_regs.h | 12 ++++
4 files changed, 85 insertions(+), 13 deletions(-)
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2.43.0
