On Mon, 2026-03-02 at 17:01 +0530, Animesh Manna wrote: > Unused bandwidth can be used by external display agents for Panel > Replay > enabled DP panel during idleness with link on. Enable source to > replace > dummy data from the display with data from another agent by > programming > TRANS_DP2_CTL [Panel Replay Tunneling Enable]. > > v2: > - Enable pr bw optimization along with panel replay enable. [Jani] > > v3: > - Write TRANS_DP2_CTL once for both bw optimization and panel replay > enable. [Jani] > > v4: > - Read DPCD once in init() and store in panel_replay_caps. [Jouni] > > v5: > - Avoid reading DPCD for edp. [Jouni] > - Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani] > > Bspec: 68920 > Reviewed-by: Arun R Murthy <[email protected]> > Signed-off-by: Animesh Manna <[email protected]> > --- > .../gpu/drm/i915/display/intel_display_regs.h | 1 + > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 35 > +++++++++++++++++-- > 4 files changed, 36 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 4746e9ebd920..dada8dc27ea4 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -2263,6 +2263,7 @@ > #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, > _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) > #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) > #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) > +#define TRANS_DP2_PR_TUNNELING_ENABLE REG_BIT(26) > #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) > > #define _TRANS_DP2_VFREQHIGH_A 0x600a4 > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8a2b37c7bccf..fbf76ad2af1c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -576,6 +576,7 @@ struct intel_connector { > > bool support; > bool su_support; > + bool optimization_support; > enum intel_panel_replay_dsc_support > dsc_support; > > u16 su_w_granularity; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 025e906b63a9..f35aafe1e86f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6250,6 +6250,7 @@ intel_dp_detect(struct drm_connector > *_connector, > intel_dp->psr.sink_panel_replay_support = false; > connector->dp.panel_replay_caps.support = false; > connector->dp.panel_replay_caps.su_support = false; > + connector->dp.panel_replay_caps.optimization_support > = false; > connector->dp.panel_replay_caps.dsc_support = > INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 5bea2eda744b..27ba96ede8e2 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -43,6 +43,7 @@ > #include "intel_dmc.h" > #include "intel_dp.h" > #include "intel_dp_aux.h" > +#include "intel_dp_tunnel.h" > #include "intel_dsb.h" > #include "intel_frontbuffer.h" > #include "intel_hdmi.h" > @@ -603,6 +604,7 @@ static void _panel_replay_init_dpcd(struct > intel_dp *intel_dp, struct intel_conn > { > struct intel_display *display = to_intel_display(intel_dp); > int ret; > + u8 val; > > /* TODO: Enable Panel Replay on MST once it's properly > implemented. */ > if (intel_dp->mst_detect == DRM_DP_MST) > @@ -650,6 +652,15 @@ static void _panel_replay_init_dpcd(struct > intel_dp *intel_dp, struct intel_conn > connector->dp.panel_replay_caps.su_support ? > "selective_update " : "", > panel_replay_dsc_support_str(connector- > >dp.panel_replay_caps.dsc_support)); > + > + if (intel_dp_is_edp(intel_dp)) > + return; > + > + /* Rest is for DP only */ > + > + drm_dp_dpcd_read_byte(&intel_dp->aux, > DP_TUNNELING_CAPABILITIES, &val); > + connector->dp.panel_replay_caps.optimization_support = val & > + DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT; > } > > static void _psr_init_dpcd(struct intel_dp *intel_dp, struct > intel_connector *connector) > @@ -1022,11 +1033,29 @@ static u8 frames_before_su_entry(struct > intel_dp *intel_dp) > return frames_before_su_entry; > } > > +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp > *intel_dp) > +{ > + struct intel_display *display = to_intel_display(intel_dp); > + struct intel_connector *connector = intel_dp- > >attached_connector; > + > + if (DISPLAY_VER(display) < 35) > + return false; > + > + if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) > + return false; > + > + if (!connector->dp.panel_replay_caps.optimization_support) > + return false; > + > + return true; > +} > + > static void dg2_activate_panel_replay(struct intel_dp *intel_dp) > { > struct intel_display *display = to_intel_display(intel_dp); > struct intel_psr *psr = &intel_dp->psr; > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > + u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE; > > if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { > u32 val = psr->su_region_et_enabled ? > @@ -1039,12 +1068,14 @@ static void dg2_activate_panel_replay(struct > intel_dp *intel_dp) > val); > } > > + if (!intel_dp_is_edp(intel_dp) && > intel_psr_allow_pr_bw_optimization(intel_dp)) > + dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE; > +
DP spec says: " The DP Source device may optionally enable PR optimization with DP tunneling. The device shall query the Tunneling Bridge’s PR tunneling optimization capability by way of the Panel_Replay_Tunneling_Optimization_Support bit in the DP_TUNNELING_CAPABILITIES register (DPCD E000Dh[6]), and then enable PR only when the Tunneling Bridge is capable. " To me it sounds like you can't enable PR if tunneling bridge isn't PR tunneling optimization capable? If this is the case then, I think you should add something into _panel_replay_compute_config. What do you think? BR, Jouni Högander > intel_de_rmw(display, > PSR2_MAN_TRK_CTL(display, intel_dp- > >psr.transcoder), > 0, > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); > > - intel_de_rmw(display, TRANS_DP2_CTL(intel_dp- > >psr.transcoder), 0, > - TRANS_DP2_PANEL_REPLAY_ENABLE); > + intel_de_rmw(display, TRANS_DP2_CTL(intel_dp- > >psr.transcoder), 0, dp2_ctl_val); > } > > static void hsw_activate_psr2(struct intel_dp *intel_dp)
