On Wed, 27 Aug 2025, Luca Coelho <[email protected]> wrote: > Use REG_BIT() instead of open coding the shift in the FW_BLC_SELF_* > macro definitions to avoid potentially typing them as 'int'. > > For example, this happens when we pass them to _MASKED_BIT_ENABLE(), > because of the typeof() construct there. When we pass 1 << 15 (the > FW_BLC_SELF_EN macro), we get typeof(1 << 15), which is 'int'. Then > the value becomes negative (-2147450880) and we try to assign it to a > 'u32'. > > In practice this is not a problem though, because when we try to > assign -2147450880 to the u32, that becomes 0x80008000, which was the > intended result. > > Signed-off-by: Luca Coelho <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > > In v2: > * changed to use REG_BIT() instead (Jani) > > > drivers/gpu/drm/i915/i915_reg.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b283b25d8368..b4188e94c9a2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -412,9 +412,9 @@ > #define FW_BLC _MMIO(0x20d8) > #define FW_BLC2 _MMIO(0x20dc) > #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ > -#define FW_BLC_SELF_EN_MASK (1 << 31) > -#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ > -#define FW_BLC_SELF_EN (1 << 15) /* 945 only */ > +#define FW_BLC_SELF_EN_MASK REG_BIT((31) > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ > #define MM_BURST_LENGTH 0x00700000 > #define MM_FIFO_WATERMARK 0x0001F000 > #define LM_BURST_LENGTH 0x00000700 -- Jani Nikula, Intel
