On Wed, 2025-08-20 at 10:14 +0530, Uma Shankar wrote: > FBC restriction where FBC is disabled for non-modulo 4 plane size > (including plane size + yoffset) is fixed from ADL onwards in h/w. > WA:22010751166 > > Relax the restriction for the same. > > Credits-to: Vidya Srinivas <[email protected]> > Signed-off-by: Uma Shankar <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index d4c5deff9cbe..bf257467a635 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1550,14 +1550,14 @@ static int intel_fbc_check_plane(struct > intel_atomic_state *state, > * having a Y offset that isn't divisible by 4 causes FIFO underrun > * and screen flicker. > */ > - if (DISPLAY_VER(display) >= 9 && > + if (DISPLAY_VER(display) >= 9 && DISPLAY_VER(display) <= 12 &&
May be use IS_DISPLAY_VER(display, 9, 12) here and below as well? Anyway, Reviewed-by: Vinod Govindapillai <[email protected]> > plane_state->view.color_plane[0].y & 3) { > plane_state->no_fbc_reason = "plane start Y offset misaligned"; > return 0; > } > > /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ > - if (DISPLAY_VER(display) >= 11 && > + if ((DISPLAY_VER(display) == 11 || DISPLAY_VER(display) == 12) && > (plane_state->view.color_plane[0].y + > (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { > plane_state->no_fbc_reason = "plane end Y offset misaligned";
