Perhaps not the ideal place, but better than having to have the fields in both struct drm_i915_private and struct xe_device.
Signed-off-by: Jani Nikula <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++---------- .../gpu/drm/i915/display/intel_display_core.h | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 3 --- drivers/gpu/drm/xe/xe_device_types.h | 2 -- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ab35ecccba63..6109f3d505c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -143,20 +143,20 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb, /* returns HPLL frequency in kHz */ int vlv_clock_get_hpll_vco(struct drm_device *drm) { - struct drm_i915_private *i915 = to_i915(drm); + struct intel_display *display = to_intel_display(drm); int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; - if (!i915->hpll_freq) { + if (!display->vlv_clock.hpll_freq) { /* Obtain SKU information */ hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK; - i915->hpll_freq = vco_freq[hpll_freq] * 1000; + display->vlv_clock.hpll_freq = vco_freq[hpll_freq] * 1000; - drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", i915->hpll_freq); + drm_dbg_kms(drm, "HPLL frequency: %d kHz\n", display->vlv_clock.hpll_freq); } - return i915->hpll_freq; + return display->vlv_clock.hpll_freq; } static int vlv_get_cck_clock(struct drm_device *drm, @@ -197,15 +197,15 @@ int vlv_clock_get_hrawclk(struct drm_device *drm) int vlv_clock_get_czclk(struct drm_device *drm) { - struct drm_i915_private *i915 = to_i915(drm); + struct intel_display *display = to_intel_display(drm); - if (!i915->czclk_freq) { - i915->czclk_freq = vlv_get_cck_clock_hpll(drm, "czclk", - CCK_CZ_CLOCK_CONTROL); - drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", i915->czclk_freq); + if (!display->vlv_clock.czclk_freq) { + display->vlv_clock.czclk_freq = vlv_get_cck_clock_hpll(drm, "czclk", + CCK_CZ_CLOCK_CONTROL); + drm_dbg_kms(drm, "CZ clock rate: %d kHz\n", display->vlv_clock.czclk_freq); } - return i915->czclk_freq; + return display->vlv_clock.czclk_freq; } int vlv_clock_get_cdclk(struct drm_device *drm) diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 8c226406c5cd..791021a4e3bb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -567,6 +567,11 @@ struct intel_display { u32 bxt_phy_grc; } state; + struct { + unsigned int hpll_freq; + unsigned int czclk_freq; + } vlv_clock; + struct { /* ordered wq for modesets */ struct workqueue_struct *modeset; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4e4e89746aa6..3a1c968e375a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -239,9 +239,6 @@ struct drm_i915_private { unsigned int fsb_freq, mem_freq, is_ddr3; - unsigned int hpll_freq; - unsigned int czclk_freq; - /** * wq - Driver workqueue for GEM. * diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 01e8fa0d2f9f..3474205a2339 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -607,8 +607,6 @@ struct xe_device { /* only to allow build, not used functionally */ struct { - unsigned int hpll_freq; - unsigned int czclk_freq; unsigned int fsb_freq, mem_freq, is_ddr3; }; #endif -- 2.39.5
