Bandwidth calculations in intel_dp_compute_link_config_wide() can lead to selecting of lower bpp (18/24). It does not account for the fact that user content can be HDR and needs 10bpc (BPP/3) for fidelity.
This can specifically happen in cases of DRRS eDP panel where we keep the link rate running according to the highest refresh rate the panel supports [1]. If such panel support 10bpc (without DSC) only at a lower refresh rate mode, the inflated link rate forces a lower BPP selection. This series takes into account the "HDR_OUTPUT_METADATA" connector property and limits the minimum BPP to 30 in case user-space sets the property with ST2084 metadata. If the required bandwidth for 30 bpp cannot be supported, the driver will either fall back to DSC or reject the mode during atomic check if DSC is not supported. This approach preserves the DRRS behaviour of the panel and makes the assumption that it will support 10bpc with all it's advertised modes atleast with DSC. [1] https://lore.kernel.org/intel-gfx/[email protected]/ Chaitanya Kumar Borah (2): drm/i915/dp: Refactor intel_dp_in_hdr_mode() for broader reuse drm/i915/dp: Set min_bpp limit to 30 in HDR mode drivers/gpu/drm/i915/display/intel_dp.c | 24 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_dp.h | 3 ++- .../drm/i915/display/intel_dp_aux_backlight.c | 13 ---------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++---- 4 files changed, 29 insertions(+), 22 deletions(-) -- 2.25.1
