> -----Original Message-----
> From: Intel-gfx <[email protected]> On Behalf Of
> Nemesa Garg
> Sent: Thursday, June 5, 2025 4:25 PM
> To: [email protected]; [email protected]
> Cc: Garg, Nemesa <[email protected]>
> Subject: [PATCH v3] drm/i915/display: Implement wa_16011342517
>
> While doing voltage swing for type-c phy for DP 1.62 and HDMI write the
> LOADGEN_SHARING_PMD_DISABLE bit to 1.
>
> -v2: Update commit.
> Add bspec[Suraj]
> -v3: Move w/a before DKL_TX_PMD_LANE_SUS.
> Use DKL_TX_DPCNTL2[Ville]
>
> Bspec: 55359
> Signed-off-by: Nemesa Garg <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 16 ++++++++++++++++
> .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 1 +
> 2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4c845dd410a2..d99d4c80fe17 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -77,6 +77,7 @@
> #include "intel_psr.h"
> #include "intel_quirks.h"
> #include "intel_snps_phy.h"
> +#include "intel_step.h"
> #include "intel_tc.h"
> #include "intel_vdsc.h"
> #include "intel_vdsc_regs.h"
> @@ -1393,6 +1394,21 @@ static void tgl_dkl_phy_set_signal_levels(struct
> intel_encoder *encoder,
> for (ln = 0; ln < 2; ln++) {
> int level;
>
> + /* Wa_16011342517:adl-p */
> + if (display->platform.alderlake_p &&
> + IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
> + if ((intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI) &&
Use intel_encoder_is_hdmi function to check if it is hdmi or not
On a side note maybe a fix can be sent for existing output check that only
Checks the output_type separate from this patch.
> + crtc_state->port_clock == 594000) ||
> + (intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_DP)
Use intel_encoder_is_dp function to check if it is dp or not
With the above fixed
Reviewed-by: Suraj Kandpal <[email protected]>
&&
> + crtc_state->port_clock == 162000)) {
> + intel_dkl_phy_rmw(display,
> DKL_TX_DPCNTL2(tc_port, ln),
> +
> LOADGEN_SHARING_PMD_DISABLE, 1);
> + } else {
> + intel_dkl_phy_rmw(display,
> DKL_TX_DPCNTL2(tc_port, ln),
> +
> LOADGEN_SHARING_PMD_DISABLE, 0);
> + }
> + }
> +
> intel_dkl_phy_write(display,
> DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
>
> level = intel_ddi_level(encoder, crtc_state, 2*ln+0); diff --git
> a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
> index 56085b32956d..ac2f92482d67 100644
> --- a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
> @@ -151,6 +151,7 @@ struct intel_dkl_phy_reg {
> #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)
> REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MAS
> K, (val))
> #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK
> REG_GENMASK(6, 5)
> #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)
> REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MAS
> K, (val))
> +#define LOADGEN_SHARING_PMD_DISABLE REG_BIT(12)
>
> #define _DKL_TX_FW_CALIB_LN0 0x02F8
> #define _DKL_TX_FW_CALIB_LN1 0x12F8
> --
> 2.25.1
