From: Ville Syrjälä <[email protected]>
Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock
gating w/a (Wa_16015201720), so don't apply it.
TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
is actuall needed, not seeing anything in the docs about it...
Reviewed-by: Uma Shankar <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index a10e56e7cf31..b6ac480f391c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -487,7 +487,7 @@ static void mtl_pipedmc_clock_gating_wa(struct
intel_display *display)
static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable)
{
- if (DISPLAY_VER(display) >= 14 && enable)
+ if (display->platform.meteorlake && enable)
mtl_pipedmc_clock_gating_wa(display);
else if (DISPLAY_VER(display) == 13)
adlp_pipedmc_clock_gating_wa(display, enable);
--
2.49.0
