> -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Ville > Syrjala > Sent: Monday, June 9, 2025 7:40 PM > To: [email protected] > Cc: [email protected] > Subject: [PATCH v4 01/21] drm/i915/dsb: Use intel_dsb_ins_align() in > intel_dsb_align_tail() > > From: Ville Syrjälä <[email protected]> > > If the free_post is not QW aligned we don't have to memset the extra DW needed > to make it so, as the only way that can happen is via > intel_dsb_reg_write_indexed() which already makes sure the next DW is zeroed. > > Not a big deal, but this is more consistent how all the other stuff operates > that puts > instructions into the DSB buffer, and we'll get a few more of those soon.
Looks Good to me. Reviewed-by: Uma Shankar <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c > b/drivers/gpu/drm/i915/display/intel_dsb.c > index 1a03c0ef2054..abda04d969c7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -528,6 +528,8 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) { > u32 aligned_tail, tail; > > + intel_dsb_ins_align(dsb); > + > tail = dsb->free_pos * 4; > aligned_tail = ALIGN(tail, CACHELINE_BYTES); > > -- > 2.49.0
