Split out display/intel_sbi_regs.h from i915_reg.h. Include both the SBI interface MMIO as well as the known sideband offsets.
Signed-off-by: Jani Nikula <[email protected]> --- .../gpu/drm/i915/display/intel_pch_refclk.c | 1 + drivers/gpu/drm/i915/display/intel_sbi.c | 2 +- drivers/gpu/drm/i915/display/intel_sbi_regs.h | 51 +++++++++++++++++++ drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 41 --------------- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 6 files changed, 55 insertions(+), 42 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_sbi_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index efa78b3883b5..88a9bdbf2f13 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -12,6 +12,7 @@ #include "intel_panel.h" #include "intel_pch_refclk.h" #include "intel_sbi.h" +#include "intel_sbi_regs.h" static void lpt_fdi_reset_mphy(struct intel_display *display) { diff --git a/drivers/gpu/drm/i915/display/intel_sbi.c b/drivers/gpu/drm/i915/display/intel_sbi.c index aea5e12519b9..c53d6058a717 100644 --- a/drivers/gpu/drm/i915/display/intel_sbi.c +++ b/drivers/gpu/drm/i915/display/intel_sbi.c @@ -7,9 +7,9 @@ #include <drm/drm_print.h> -#include "i915_reg.h" #include "intel_de.h" #include "intel_sbi.h" +#include "intel_sbi_regs.h" /* SBI access */ static int intel_sbi_rw(struct intel_display *display, u16 reg, diff --git a/drivers/gpu/drm/i915/display/intel_sbi_regs.h b/drivers/gpu/drm/i915/display/intel_sbi_regs.h new file mode 100644 index 000000000000..38963f8619a3 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sbi_regs.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef __INTEL_SBI_REGS_H__ +#define __INTEL_SBI_REGS_H__ + +#include "i915_reg_defs.h" + +/* + * Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which + * contains the register offset; and SBI_DATA, which contains the payload. + */ +#define SBI_ADDR _MMIO(0xC6000) +#define SBI_DATA _MMIO(0xC6004) +#define SBI_CTL_STAT _MMIO(0xC6008) +#define SBI_CTL_DEST_ICLK (0x0 << 16) +#define SBI_CTL_DEST_MPHY (0x1 << 16) +#define SBI_CTL_OP_IORD (0x2 << 8) +#define SBI_CTL_OP_IOWR (0x3 << 8) +#define SBI_CTL_OP_CRRD (0x6 << 8) +#define SBI_CTL_OP_CRWR (0x7 << 8) +#define SBI_RESPONSE_FAIL (0x1 << 1) +#define SBI_RESPONSE_SUCCESS (0x0 << 1) +#define SBI_BUSY (0x1 << 0) +#define SBI_READY (0x0 << 0) + +/* SBI offsets */ +#define SBI_SSCDIVINTPHASE 0x0200 +#define SBI_SSCDIVINTPHASE6 0x0600 +#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 +#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) +#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) +#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 +#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) +#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) +#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) +#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) +#define SBI_SSCDITHPHASE 0x0204 +#define SBI_SSCCTL 0x020c +#define SBI_SSCCTL6 0x060C +#define SBI_SSCCTL_PATHALT (1 << 3) +#define SBI_SSCCTL_DISABLE (1 << 0) +#define SBI_SSCAUXDIV6 0x0610 +#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 +#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) +#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) +#define SBI_DBUFF0 0x2a00 +#define SBI_GEN0 0x1f00 +#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) + +#endif /* __INTEL_SBI_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 1344e6d20a34..7ee0e3657321 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -55,6 +55,7 @@ #include "display/intel_fdi_regs.h" #include "display/intel_pps_regs.h" #include "display/intel_psr_regs.h" +#include "display/intel_sbi_regs.h" #include "display/intel_sprite_regs.h" #include "display/intel_vga_regs.h" #include "display/skl_universal_plane_regs.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2e4190da3e0d..c1a7ac466828 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3588,47 +3588,6 @@ enum skl_power_gate { #define _DDI_DP_COMP_PAT_B 0x615F4 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) -/* Sideband Interface (SBI) is programmed indirectly, via - * SBI_ADDR, which contains the register offset; and SBI_DATA, - * which contains the payload */ -#define SBI_ADDR _MMIO(0xC6000) -#define SBI_DATA _MMIO(0xC6004) -#define SBI_CTL_STAT _MMIO(0xC6008) -#define SBI_CTL_DEST_ICLK (0x0 << 16) -#define SBI_CTL_DEST_MPHY (0x1 << 16) -#define SBI_CTL_OP_IORD (0x2 << 8) -#define SBI_CTL_OP_IOWR (0x3 << 8) -#define SBI_CTL_OP_CRRD (0x6 << 8) -#define SBI_CTL_OP_CRWR (0x7 << 8) -#define SBI_RESPONSE_FAIL (0x1 << 1) -#define SBI_RESPONSE_SUCCESS (0x0 << 1) -#define SBI_BUSY (0x1 << 0) -#define SBI_READY (0x0 << 0) - -/* SBI offsets */ -#define SBI_SSCDIVINTPHASE 0x0200 -#define SBI_SSCDIVINTPHASE6 0x0600 -#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 -#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) -#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) -#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 -#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) -#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) -#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) -#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) -#define SBI_SSCDITHPHASE 0x0204 -#define SBI_SSCCTL 0x020c -#define SBI_SSCCTL6 0x060C -#define SBI_SSCCTL_PATHALT (1 << 3) -#define SBI_SSCCTL_DISABLE (1 << 0) -#define SBI_SSCAUXDIV6 0x0610 -#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 -#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) -#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) -#define SBI_DBUFF0 0x2a00 -#define SBI_GEN0 0x1f00 -#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) - /* LPT PIXCLK_GATE */ #define PIXCLK_GATE _MMIO(0xC6020) #define PIXCLK_GATE_UNGATE (1 << 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index d581a9d2c063..cf3ff16e630e 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -20,6 +20,7 @@ #include "display/intel_lvds_regs.h" #include "display/intel_pfit_regs.h" #include "display/intel_psr_regs.h" +#include "display/intel_sbi_regs.h" #include "display/intel_sprite_regs.h" #include "display/intel_vga_regs.h" #include "display/skl_universal_plane_regs.h" -- 2.39.5
