Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

Signed-off-by: Mitul Golani <[email protected]>
Reviewed-by: Ankit Nautiyal <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index dcaae7631b0a..420ee917d6a9 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -483,6 +483,8 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(crtc_state);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       enum pipe pipe = crtc->pipe;
 
        /*
         * This bit seems to have two meanings depending on the platform:
@@ -510,6 +512,24 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
                               lower_32_bits(crtc_state->cmrr.cmrr_n));
        }
 
+       if (HAS_VRR_DC_BALANCE(display) &&
+           (crtc_state->vrr.dc_balance.vmin || 
crtc_state->vrr.dc_balance.vmax)) {
+               intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+                              crtc_state->vrr.dc_balance.vmin - 1);
+               intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+                              crtc_state->vrr.dc_balance.vmax - 1);
+               intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+                              crtc_state->vrr.dc_balance.max_increase);
+               intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+                              crtc_state->vrr.dc_balance.max_decrease);
+               intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+                              crtc_state->vrr.dc_balance.guardband);
+               intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+                              crtc_state->vrr.dc_balance.slope);
+               intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+                              crtc_state->vrr.dc_balance.vblank_target);
+       }
+
        intel_vrr_set_fixed_rr_timings(crtc_state);
 
        if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable)
-- 
2.48.1

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