> -----Original Message----- > From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of Jouni > Högander > Sent: Friday, 7 March 2025 12.52 > To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org > Cc: Hogander, Jouni <jouni.hogan...@intel.com> > Subject: [RFC PATCH 03/11] drm/i915/dmc: Add PIPEDMC_EVT_CTL register > definition > > To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) > we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register > definitions. > > Bspec: 67576 >
Reviewed-by: Mika Kahola <mika.kah...@intel.com> > Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h > b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > index 1bf446f96a10..2f1e3cb1a247 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > @@ -21,6 +21,12 @@ > #define MTL_PIPEDMC_CONTROL _MMIO(0x45250) > #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4) > > +#define _MTL_PIPEDMC_EVT_CTL_4_A 0x5f044 > +#define _MTL_PIPEDMC_EVT_CTL_4_B 0x5f444 > +#define MTL_PIPEDMC_EVT_CTL_4(pipe) _MMIO_PIPE(pipe, > \ > + > _MTL_PIPEDMC_EVT_CTL_4_A, \ > + > _MTL_PIPEDMC_EVT_CTL_4_B) > + > #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 > #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 > > -- > 2.43.0
