Disable FBC compressor clock gating before enabling FBC and clear it after disabling FBC.
Bspec: 74212, 69741, 65555 Signed-off-by: Vinod Govindapillai <[email protected]> --- drivers/gpu/drm/i915/display/intel_fbc.c | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index df05904bac8a..637fe8c04cb6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -522,6 +522,13 @@ static void ilk_fbc_activate(struct intel_fbc *fbc) DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); } +static void mtl_fbc_compressor_clkgate_disable(struct intel_fbc *fbc, + bool disable) +{ + intel_de_rmw(fbc->display, MTL_PIPE_CLKGATE_DIS2(fbc->id), + MTL_DPFC_GATING_DIS, disable ? MTL_DPFC_GATING_DIS : 0); +} + static void ilk_fbc_deactivate(struct intel_fbc *fbc) { struct intel_display *display = fbc->display; @@ -532,6 +539,10 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) if (dpfc_ctl & DPFC_CTL_EN) { dpfc_ctl &= ~DPFC_CTL_EN; intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + + /* wa_18038517565 Enable DPFC clock gating after FBC disable */ + if (DISPLAY_VER(display) >= 14 || display->platform.dg2) + mtl_fbc_compressor_clkgate_disable(fbc, false); } } @@ -665,6 +676,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (intel_fbc_has_fences(display)) snb_fbc_program_fence(fbc); + /* wa_18038517565 Disable DPFC clock gating before FBC enable */ + if (DISPLAY_VER(display) >= 14 || display->platform.dg2) + mtl_fbc_compressor_clkgate_disable(fbc, true); + /* wa_14019417088 Alternative WA*/ dpfc_ctl = ivb_dpfc_ctl(fbc); if (DISPLAY_VER(display) >= 20) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 03da51b03fb9..236188a1c9ce 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4269,6 +4269,12 @@ enum skl_power_gate { #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) +#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114 +#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114 +#define MTL_PIPE_CLKGATE_DIS2(pipe) \ + _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B) +#define MTL_DPFC_GATING_DIS REG_BIT(6) + #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) -- 2.43.0
