From: Akash Goel <[email protected]> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'. This workaround has to be applied before doing TLB Invalidation on render ring. In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI Store data commands. Without this, hardware cannot guarantee the command after the PIPE_CONTROL with TLB inv will not use the old TLB values.
v2: Modified the WA comment (Ville) v3: Added the vlv identifier with WA name (Damien) v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func, sending 6 dwords instead of 8) (Chris) v5: Enhancing the scope of WA to gen6, gen7. Having a common WA func being called from gen6, gen7 flush functions. (Ville) v6: WA is applicable only to render ring, earlier put for all rings in v5. (Chris) Signed-off-by: Sourab Gupta <[email protected]> Signed-off-by: Akash Goel <[email protected]> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 87d1a2d..816137f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -208,6 +208,31 @@ intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) } static int +gen6_tlb_invalidate_wa(struct intel_ring_buffer *ring) +{ + /* + * WaTlbInvalidateStoreDataBefore:gen6,gen7 + * This workaround has to be applied before doing TLB invalidation + * on the render ring. Before pipecontrol with TLB invalidate set, + * need 2 store data commands (such as MI_STORE_DATA_IMM or + * MI_STORE_DATA_INDEX). Without this, hardware cannot guarantee + * the command after the PIPE_CONTROL with TLB inv will not use + * the old TLB values. + */ + int i, ret; + ret = intel_ring_begin(ring, 3 * 2); + if (ret) + return ret; + for (i = 0; i < 2; i++) { + intel_ring_emit(ring, MI_STORE_DWORD_INDEX); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); + return 0; +} + +static int gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) { @@ -215,6 +240,13 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate_domains) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + /* Force SNB workarounds for PIPE_CONTROL flushes */ ret = intel_emit_post_sync_nonzero_flush(ring); if (ret) @@ -309,6 +341,13 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = ring->scratch.gtt_offset + 128; int ret; + /* Apply WaTlbInvalidateStoreDataBefore workaround */ + if (invalidate_domains) { + ret = gen6_tlb_invalidate_wa(ring); + if (ret) + return ret; + } + /* * Ensure that any following seqno writes only happen when the render * cache is indeed flushed. -- 1.8.5.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
