On Fri, 2014-03-21 at 17:18 +0000, Chris Wilson wrote: > The documentation calls this GFX_MODE bit "Flush TLB invalidate Mode". > However, that is not a good name for an enable bit as it doesn't make it > clear what is enabled. An even worse name is GFX_TLB_INVALIDATE_ALWAYS > as enabling that bit actually prevents the TLB from being invalidated at > every flush. This leads to great confusion when reading code and > proposed patches. To get around this try to bake in what is enabled by > setting the bit and call it GFX_TLB_INVALIDATE_EXPLICIT. >
This looks fine. It clears the confusion around TLB INVALIDATE Bit. We'll be developing our patch on top of this and sending the full series of WA patches for VLV. > Signed-off-by: Chris Wilson <[email protected]> > Cc: "Gupta, Sourab" <[email protected]> > --- > Alternatively, we could call it GFX_TLB_INVALIDATE_MANUAL. > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9476b483417a..cd5ac2e03c7e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -843,7 +843,7 @@ enum punit_power_well { > #define GFX_MODE_GEN7 0x0229c > #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) > #define GFX_RUN_LIST_ENABLE (1<<15) > -#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) > +#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) > #define GFX_SURFACE_FAULT_ENABLE (1<<12) > #define GFX_REPLAY_MODE (1<<11) > #define GFX_PSMI_GRANULARITY (1<<10) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 99b1d8e15711..9470e51f0c9f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -595,11 +595,11 @@ static int init_render_ring(struct intel_ring_buffer > *ring) > /* Required for the hardware to program scanline values for waiting */ > if (INTEL_INFO(dev)->gen == 6) > I915_WRITE(GFX_MODE, > - _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); > + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); > > if (IS_GEN7(dev)) > I915_WRITE(GFX_MODE_GEN7, > - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > + _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_EXPLICIT) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > > if (INTEL_INFO(dev)->gen >= 5) { > @@ -622,7 +622,7 @@ static int init_render_ring(struct intel_ring_buffer > *ring) > * TODO: consider explicitly setting the bit for GEN5 > */ > ring->itlb_before_ctx_switch = > - !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); > + !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_EXPLICIT); > } > > if (INTEL_INFO(dev)->gen >= 6) _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
