It was observed that the first write to DKL DP Mode register
was not taking effect, hence rewrite this register.
Signed-off-by: Nemesa Garg <nemesa.g...@intel.com>
Signed-off-by: Kulkarni, Vandita <vandita.kulka...@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 769bd1f26db2..16a1d18f3aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2104,6 +2104,16 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct
intel_encoder *encoder)
encoder->disable_clock(encoder);
}
+static void
+tgl_wa_14018221282(struct drm_i915_private *dev_priv, enum tc_port tc_port,
+ u32 ln0, u32 ln1)
+{
+ if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
+ intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+ if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
+ intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+}
+
static void
icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
@@ -2185,6 +2195,10 @@ icl_program_mg_dp_mode(struct intel_digital_port
*dig_port,
if (DISPLAY_VER(dev_priv) >= 12) {
intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+ /* WA_14018221282 */
+ if (DISPLAY_VER(dev_priv) == 12)
+ tgl_wa_14018221282(dev_priv, tc_port, ln0, ln1);
+
} else {
intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
--
2.25.1
