[PATCH 2/4] drm/i915/dp: Export intel_ddi_config_transcoder_dp2()

[Imre Deak]

Export intel_ddi_config_transcoder_dp2() taken into use by the MST
encoder in the next patch. Move the HAS_DP20() check to the function, so
it doesn't need to be checked for each caller. Besides enabling the DP2
configuration also add a way to disable it, required by the MST slave
transcoder disabling sequence in the next patch.

Signed-off-by: Imre Deak <imre.d...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++------
 drivers/gpu/drm/i915/display/intel_ddi.h |  3 +++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6bbfe0762cafa..5ff7d23775d82 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -454,15 +454,19 @@ static u32 bdw_trans_port_sync_master_select(enum 
transcoder master_transcoder)
                return master_transcoder + 1;
 }
 
-static void
+void
 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
-                               const struct intel_crtc_state *crtc_state)
+                               const struct intel_crtc_state *crtc_state,
+                               bool enable)
 {
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        u32 val = 0;
 
-       if (intel_dp_is_uhbr(crtc_state))
+       if (!HAS_DP20(i915))
+               return;
+
+       if (enable && intel_dp_is_uhbr(crtc_state))
                val = TRANS_DP2_128B132B_CHANNEL_CODING;
 
        intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
@@ -2549,7 +2553,7 @@ static void mtl_ddi_pre_enable_dp(struct 
intel_atomic_state *state,
        /*
         * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
         */
-       intel_ddi_config_transcoder_dp2(encoder, crtc_state);
+       intel_ddi_config_transcoder_dp2(encoder, crtc_state, true);
 
        /*
         * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
@@ -2686,8 +2690,7 @@ static void tgl_ddi_pre_enable_dp(struct 
intel_atomic_state *state,
         */
        intel_ddi_enable_transcoder_clock(encoder, crtc_state);
 
-       if (HAS_DP20(dev_priv))
-               intel_ddi_config_transcoder_dp2(encoder, crtc_state);
+       intel_ddi_config_transcoder_dp2(encoder, crtc_state, true);
 
        /*
         * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h 
b/drivers/gpu/drm/i915/display/intel_ddi.h
index 1aa2e3a190aee..bf27b2fbb08e9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -65,6 +65,9 @@ void intel_ddi_disable_transcoder_func(const struct 
intel_crtc_state *crtc_state
 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
                                       const struct intel_crtc_state 
*crtc_state);
 void intel_ddi_disable_transcoder_clock(const  struct intel_crtc_state 
*crtc_state);
+void intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
+                                    const struct intel_crtc_state *crtc_state,
+                                    bool enable);
 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
                                   const struct intel_crtc_state *crtc_state,
                                   bool enabled);
-- 
2.44.2