Store the CCS mode value in the intel_gt->ccs structure to make it available for future instances that may need to change its value.
Name it mode_reg_val because it holds the value that will be written into the CCS_MODE register, determining the CCS balancing and, consequently, the number of engines generated. Create a mutex to control access to the mode_reg_val variable. No functional changes intended. Signed-off-by: Andi Shyti <[email protected]> --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 10 +++++++--- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 12 ++++++++++++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++--- 4 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 0710e55d37d7..8acb9ee5b511 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -18,6 +18,8 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) unsigned int i; u8 first_ccs; + mutex_init(>->ccs.mutex); + /* Calculate the slices considering the fused engines */ ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; fused_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, @@ -55,14 +57,16 @@ void intel_gt_ccs_mode_init(struct intel_gt *gt) info->engine_mask |= BIT(_CCS(first_ccs)); } -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) +void intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); + lockdep_assert_held(>->ccs.mutex); + if (!IS_DG2(gt->i915)) - return 0; + return; /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { @@ -82,7 +86,7 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - return mode; + gt->ccs.mode_reg_val = mode; } static ssize_t num_cslices_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index b9ce29055857..5793c4178bd9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,7 +8,7 @@ struct intel_gt; -unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); +void intel_gt_apply_ccs_mode(struct intel_gt *gt); void intel_gt_sysfs_ccs_init(struct intel_gt *gt); void intel_gt_ccs_mode_init(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 3c9fae53871a..ef803ace41a3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -207,12 +207,24 @@ struct intel_gt { [MAX_ENGINE_INSTANCE + 1]; enum intel_submission_method submission_method; + /* + * Track fixed mapping between CCS engines and compute slices. + * + * In order to w/a HW that has the inability to dynamically load + * balance between CCS engines and EU in the compute slices, we have to + * reconfigure a static mapping on the fly. + * + * The mode variable is set by the user and sets the balancing mode, + * i.e. how the CCS streams are distributed amongs the slices. + */ struct { /* * Mask of the non fused CCS slices * to be used for the load balancing */ + struct mutex mutex; intel_engine_mask_t cslice_mask; + u32 mode_reg_val; } ccs; /* diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 09a287c1aedd..379b3dde3bbd 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2713,7 +2713,6 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; - u32 mode; if (!IS_DG2(gt->i915)) return; @@ -2730,8 +2729,10 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 */ - mode = intel_gt_apply_ccs_mode(gt); - wa_masked_en(wal, XEHP_CCS_MODE, mode); + mutex_lock(>->ccs.mutex); + intel_gt_apply_ccs_mode(gt); + wa_masked_en(wal, XEHP_CCS_MODE, gt->ccs.mode_reg_val); + mutex_unlock(>->ccs.mutex); } /* -- 2.45.2
