On Wed, Jan 17, 2024 at 12:12:18PM +0200, Lisovskiy, Stanislav wrote:
> On Fri, Jan 12, 2024 at 07:35:24PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 28, 2023 at 10:37:53AM +0200, Stanislav Lisovskiy wrote:
> > > We need that in order to force disable SAGV in next patch.
> > > Also it is beneficial to separate that code, as in majority cases,
> > > when SAGV is enabled, we don't even need those calculations.
> > > Also we probably need to determine max PSF GV point as well, however
> > > currently we don't do that when we disable SAGV, which might be
> > > actually causing some issues in that case.
> > > 
> > > Signed-off-by: Stanislav Lisovskiy <[email protected]>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++-----
> > >  1 file changed, 65 insertions(+), 17 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> > > b/drivers/gpu/drm/i915/display/intel_bw.c
> > > index 583cd2ebdf89..efd408e96e8a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > @@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state 
> > > *state)
> > >   return to_intel_bw_state(bw_state);
> > >  }
> > >  
> > > +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
> > > +                                  int num_active_planes)
> > > +{
> > > + unsigned int max_bw_point = 0;
> > > + unsigned int max_bw = 0;
> > > + unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > > + int i;
> > > +
> > > + for (i = 0; i < num_qgv_points; i++) {
> > > +         unsigned int idx;
> > > +         unsigned int max_data_rate;
> > > +
> > > +         if (DISPLAY_VER(i915) > 11)
> > > +                 idx = tgl_max_bw_index(i915, num_active_planes, i);
> > > +         else
> > > +                 idx = icl_max_bw_index(i915, num_active_planes, i);
> > > +
> > > +         if (idx >= ARRAY_SIZE(i915->display.bw.max))
> > > +                 continue;
> > > +
> > > +         max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> > 
> > Looks like that that part could be extracted to a helper
> > to be used by both codepaths (would be a natural counterpart
> > to adl_psf_bw()).
> > 
> > > +
> > > +         /*
> > > +          * We need to know which qgv point gives us
> > > +          * maximum bandwidth in order to disable SAGV
> > > +          * if we find that we exceed SAGV block time
> > > +          * with watermarks. By that moment we already
> > > +          * have those, as it is calculated earlier in
> > > +          * intel_atomic_check,
> > > +          */
> > > +         if (max_data_rate > max_bw) {
> > > +                 max_bw_point = i;
> > > +                 max_bw = max_data_rate;
> > > +         }
> > > + }
> > > +
> > > + return max_bw_point;
> > > +}
> > > +
> > > +unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915)
> > > +{
> > > + unsigned int num_psf_gv_points = 
> > > i915->display.bw.max[0].num_psf_gv_points;
> > > + unsigned int max_bw = 0;
> > > + unsigned int max_bw_point = 0;
> > > + int i;
> > > +
> > > + for (i = 0; i < num_psf_gv_points; i++) {
> > > +         unsigned int max_data_rate = adl_psf_bw(i915, i);
> > > +
> > > +         if (max_data_rate > max_bw) {
> > > +                 max_bw_point = i;
> > > +                 max_bw = max_data_rate;
> > > +         }
> > > + }
> > > +
> > > + return max_bw_point;
> > > +}
> > > +
> > >  static int mtl_find_qgv_points(struct drm_i915_private *i915,
> > >                          unsigned int data_rate,
> > >                          unsigned int num_active_planes,
> > > @@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct 
> > > drm_i915_private *i915,
> > >                          const struct intel_bw_state *old_bw_state,
> > >                          struct intel_bw_state *new_bw_state)
> > >  {
> > > - unsigned int max_bw_point = 0;
> > > - unsigned int max_bw = 0;
> > >   unsigned int num_psf_gv_points = 
> > > i915->display.bw.max[0].num_psf_gv_points;
> > >   unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
> > >   u16 psf_points = 0;
> > > @@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct 
> > > drm_i915_private *i915,
> > >  
> > >           max_data_rate = i915->display.bw.max[idx].deratedbw[i];
> > >  
> > > -         /*
> > > -          * We need to know which qgv point gives us
> > > -          * maximum bandwidth in order to disable SAGV
> > > -          * if we find that we exceed SAGV block time
> > > -          * with watermarks. By that moment we already
> > > -          * have those, as it is calculated earlier in
> > > -          * intel_atomic_check,
> > > -          */
> > > -         if (max_data_rate > max_bw) {
> > > -                 max_bw_point = i;
> > > -                 max_bw = max_data_rate;
> > > -         }
> > >           if (max_data_rate >= data_rate)
> > >                   qgv_points |= BIT(i);
> > >  
> > > @@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct 
> > > drm_i915_private *i915,
> > >    * cause.
> > >    */
> > >   if (!intel_can_enable_sagv(i915, new_bw_state)) {
> > > -         qgv_points = BIT(max_bw_point);
> > > -         drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n",
> > > -                     max_bw_point);
> > > +         unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 
> > > num_active_planes);
> > > +         unsigned int max_bw_psf_gv_point = 
> > > icl_max_bw_psf_gv_point(i915);
> > > +
> > > +         qgv_points = BIT(max_bw_qgv_point);
> > > +         psf_points = BIT(max_bw_psf_gv_point);
> > 
> > We didn't restrict the PSF here previously.
> 
> Yep, but I really suspect we should. BSpec states that we should restrict all 
> the GV points
> except highest one, also that some PSF GV points aren't same or usable, 
> depending on BW reqs.
> So I would restrict that as well, in case if SAGV is off, just to be on safe 
> side.

Pretty sure it's explicitly noted that PSF doesn't cause issues with
latency and hence doesn't need this.

In any case, a change like this has no business being in a patch
that's just supposed to refactor code.

-- 
Ville Syrjälä
Intel

Reply via email to