Quoting Ville Syrjala (2023-11-28 08:51:35-03:00) >From: Ville Syrjälä <[email protected]> > >Allow MTL to use voltage level 1 for 480MHz cdclk, >instead of the voltage level 2 that it's currently using. > >Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Gustavo Sousa <[email protected]> >--- > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c >b/drivers/gpu/drm/i915/display/intel_cdclk.c >index 6f0a050ad663..f6446102490d 100644 >--- a/drivers/gpu/drm/i915/display/intel_cdclk.c >+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c >@@ -3512,7 +3512,7 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = { > .get_cdclk = bxt_get_cdclk, > .set_cdclk = bxt_set_cdclk, > .modeset_calc_cdclk = bxt_modeset_calc_cdclk, >- .calc_voltage_level = tgl_calc_voltage_level, >+ .calc_voltage_level = rplu_calc_voltage_level, > }; > > static const struct intel_cdclk_funcs rplu_cdclk_funcs = { >-- >2.41.0 >
