On Fri, Sep 01, 2023 at 10:27:00AM +0530, Shekhar Chauhan wrote: > Disables Atomic-chaining of Typed Writes. > > BSpec: 54040 > Signed-off-by: Shekhar Chauhan <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 0e4c638fcbbf..a00ff51c681d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1218,6 +1218,8 @@ > > #define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0) > #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, > 11) > +#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) > + > #define ICL_HDC_MODE MCR_REG(0xe5f4) > > #define EU_PERF_CNTL2 PERF_REG(0xe658) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 864d41bcf6bb..70071ead0659 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2327,6 +2327,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > > LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); > } > > + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || > + IS_DG2(i915)) { > + /* Wa_14015150844 */ > + wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0, > + _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), > + 0, true); > + } > + > if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) { > /* Wa_22014600077:dg2 */ > wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
