Reviewed-by: Rodrigo Vivi <[email protected]> On Wed, Jan 22, 2014 at 5:32 PM, <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > WaApplyL3ControlAndL3ChickenMode is only relevant to early HSW > steppings.. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_pm.c | 6 ------ > 1 file changed, 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 70f3b2b..0d9ded4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4762,12 +4762,6 @@ static void haswell_init_clock_gating(struct > drm_device *dev) > > ilk_init_lp_watermarks(dev); > > - /* WaApplyL3ControlAndL3ChickenMode:hsw */ > - I915_WRITE(GEN7_L3CNTLREG1, > - GEN7_WA_FOR_GEN7_L3_CONTROL); > - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, > - GEN7_WA_L3_CHICKEN_MODE); > - > /* L3 caching of data atomics doesn't work -- disable it. */ > I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); > I915_WRITE(HSW_ROW_CHICKEN3, > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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