Hi Gustavo, > -----Original Message----- > From: Sousa, Gustavo <[email protected]> > Sent: Monday, May 15, 2023 7:45 AM > To: Sripada, Radhakrishna <[email protected]>; intel- > [email protected] > Cc: Justen, Jordan L <[email protected]>; Sripada, Radhakrishna > <[email protected]>; Kalvala, Haridhar > <[email protected]>; Roper, Matthew D > <[email protected]> > Subject: Re: [PATCH v2 1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL A- > step > > Quoting Radhakrishna Sripada (2023-05-12 23:14:37) > >The dg2 workaround which is used for performance tuning > >is needed for Meteorlake A-step. > > > >v2: Limit the WA for A-step > > I think what Matt meant in the review for v1 was that this commit should > be rather about the tuning setting rather than the workaround itself. As > such, maybe we should change the commit message so that it focus on the > recommended tuning setting, i.e., instead of "Extend Wa_16014892111 to > MTL A-step" as subject, we should write something like "Apply > recommended tuning setting for ..." and give details. > > That said, since we are focusing on the tuning settings here, I guess > this could be squashed with the second patch and we could add a note > about DRAW_WATERMARK needing Wa_16014892111 for A steps of MTL.
There are 2 aspects wrt. DRAW_WATERMARK. One that is a workaround which is applied on each context switch and is only applicable for DG2 and MTL-A step which is what this patch does. The other is the tuning parameter setting which is applicable for all of MTL which is a onetime configuration Handled by the next patch during ctx_workarounds_init. - Radhakrishna Sripada > > -- > Gustavo Sousa > > > > >Bspec: 68331 > >Cc: Haridhar Kalvala <[email protected]> > >Cc: Matt Roper <[email protected]> > >Cc: Gustavo Sousa <[email protected]> > >Signed-off-by: Radhakrishna Sripada <[email protected]> > >--- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > >index 81a96c52a92b..9c1007c44298 100644 > >--- a/drivers/gpu/drm/i915/gt/intel_lrc.c > >+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > >@@ -1370,7 +1370,9 @@ gen12_emit_indirect_ctx_rcs(const struct > intel_context *ce, u32 *cs) > > cs, GEN12_GFX_CCS_AUX_NV); > > > > /* Wa_16014892111 */ > >- if (IS_DG2(ce->engine->i915)) > >+ if (IS_DG2(ce->engine->i915) || > >+ IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || > >+ IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0)) > > cs = dg2_emit_draw_watermark_setting(cs); > > > > return cs; > >-- > >2.34.1 > >
