On Thu, May 04, 2023 at 02:10:38AM +0300, Imre Deak wrote: > Make sure that the CRTC state is reset correctly, as expected after > disabling the CRTC. > > In particular this change will: > - Zero all the CSC blob pointers after intel_crtc_free_hw_state() > has freed them. > - Zero the shared DPLL and port PLL pointers and clear the > corresponding active flags in the PLL state. > - Reset all the transcoder and pipe fields. > > v2: > - Reset fully the CRTC state. (Ville) > - Clear pipe active flags in the DPLL state. > > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_modeset_setup.c | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c > index eefa4018dc0c2..2ca66e49d8863 100644 > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c > @@ -88,13 +88,14 @@ static void intel_crtc_disable_noatomic(struct intel_crtc > *crtc, > crtc->active = false; > crtc->base.enabled = false; > > - drm_WARN_ON(&i915->drm, > - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); > - crtc_state->uapi.active = false; > - crtc_state->uapi.connector_mask = 0; > - crtc_state->uapi.encoder_mask = 0; > + if (crtc_state->shared_dpll) { > + crtc_state->shared_dpll->state.pipe_mask &= ~BIT(pipe);
So that's basiclly unreference_shared_dpll(). I wonder if we can refactor that a bit to by usable here? > + crtc_state->shared_dpll->active_mask &= ~BIT(pipe); > + } Isn't this part of disable_shared_dpll()? Are we not calling that? > + > + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); > intel_crtc_free_hw_state(crtc_state); > - memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); > + intel_crtc_state_reset(crtc_state, crtc); > > for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) > encoder->base.crtc = NULL; > -- > 2.37.2 -- Ville Syrjälä Intel
