Thank you for the review. Merged both the workarounds with updated Bspec page.
- Radhakrishna(RK) Sripada > -----Original Message----- > From: Atwood, Matthew S <[email protected]> > Sent: Wednesday, April 19, 2023 2:49 PM > To: Sripada, Radhakrishna <[email protected]>; intel- > [email protected] > Cc: [email protected] > Subject: Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl: WA to clear RDOP clock > gating > > On Tue, Apr 18, 2023 at 03:04:46PM -0700, Radhakrishna Sripada wrote: > > From: Haridhar Kalvala <[email protected]> > > > > Workaround implementation to clear RDOP clock gating. > > > > Bspec: 33453 > A better bspec value here is 53509, you're referencing a non-updating > page > > > With that. > Reviewed-by: Matt Atwood <[email protected]> > > Signed-off-by: Haridhar Kalvala <[email protected]> > > Signed-off-by: Radhakrishna Sripada <[email protected]> > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index b925ef47304b..312eb8b5f949 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -1703,6 +1703,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, > struct i915_wa_list *wal) > > /* Wa_18018781329 */ > > wa_mcr_write_or(wal, RENDER_MOD_CTRL, > FORCE_MISS_FTLB); > > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); > > + > > + /* Wa_14015795083 */ > > + wa_write_clr(wal, GEN7_MISCCPCTL, > GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > > } > > > > /* > > -- > > 2.34.1 > >
