On Wed, Mar 22, 2023 at 03:01:38AM +0200, Vinod Govindapillai wrote: > Wrong register address is used to read the SAG block time. Fix > the register address according to the bspec. > > Bspec: 64608 > > Signed-off-by: Vinod Govindapillai <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ae8ba090c0f4..b2ed3c0fee4c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7716,7 +7716,7 @@ enum skl_power_gate { > #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) > #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) > > -#define MTL_LATENCY_SAGV _MMIO(0x4578b)
I'm again thinking that it would nice to have the code validate that our register offsets are actually sane. We had one other case like this in the past, which was an FBC registers where bspec had basically an ocr bug (B vs. 8). > +#define MTL_LATENCY_SAGV _MMIO(0x4578c) > #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) > > #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) > -- > 2.34.1 -- Ville Syrjälä Intel
