On Mon, Jan 30, 2023 at 09:34:22AM -0800, Matt Roper wrote: > On Mon, Jan 30, 2023 at 12:19:48PM -0500, Rodrigo Vivi wrote: > > On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote: > > > Several post-DG1 platforms have been brought up now, so we're well past > > > the point where we usually drop the workarounds that are only applicable > > > to internal/pre-production hardware. > > > > > > Production DG1 hardware always has a B0 stepping for both display and > > > GT. > > > > > > Bspec: 44463 > > > Signed-off-by: Matt Roper <[email protected]> > > > --- > > > .../drm/i915/display/intel_display_power.c | 1 - > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++----------------- > > > drivers/gpu/drm/i915/i915_driver.c | 1 + > > > drivers/gpu/drm/i915/i915_drv.h | 2 - > > > drivers/gpu/drm/i915/intel_pm.c | 12 ----- > > > 5 files changed, 5 insertions(+), 59 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > > > b/drivers/gpu/drm/i915/display/intel_display_power.c > > > index 1dc31f0f5e0a..7222502a760c 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > > @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct > > > drm_i915_private *dev_priv) > > > return; > > > > > > if (IS_ALDERLAKE_S(dev_priv) || > > > - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || > > > IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > > /* Wa_1409767108 */ > > > table = wa_1409767108_buddy_page_masks; > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > index 82a8f372bde6..648fceba5bb6 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, > > > struct i915_wa_list *wal) > > > > > > gen12_gt_workarounds_init(gt, wal); > > > > > > - /* Wa_1607087056:dg1 */ > > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) > > > - wa_write_or(wal, > > > - GEN11_SLICE_UNIT_LEVEL_CLKGATE, > > > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); > > > - > > > /* Wa_1409420604:dg1 */ > > > if (IS_DG1(i915)) > > > wa_mcr_write_or(wal, > > > @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct > > > intel_engine_cs *engine) > > > } > > > } > > > > > > -static void dg1_whitelist_build(struct intel_engine_cs *engine) > > > -{ > > > - struct i915_wa_list *w = &engine->whitelist; > > > - > > > - tgl_whitelist_build(engine); > > > - > > > - /* GEN:BUG:1409280441:dg1 */ > > > - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && > > > - (engine->class == RENDER_CLASS || > > > - engine->class == COPY_ENGINE_CLASS)) > > > - whitelist_reg_ext(w, RING_ID(engine->mmio_base), > > > - RING_FORCE_TO_NONPRIV_ACCESS_RD); > > > -} > > > - > > > static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) > > > { > > > allow_read_ctx_timestamp(engine); > > > @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct > > > intel_engine_cs *engine) > > > dg2_whitelist_build(engine); > > > else if (IS_XEHPSDV(i915)) > > > xehpsdv_whitelist_build(engine); > > > - else if (IS_DG1(i915)) > > > - dg1_whitelist_build(engine); > > > else if (GRAPHICS_VER(i915) == 12) > > > tgl_whitelist_build(engine); > > > else if (GRAPHICS_VER(i915) == 11) > > > @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, > > > struct i915_wa_list *wal) > > > true); > > > } > > > > > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { > > > - /* > > > - * Wa_1607138336 > > > - * Wa_1607063988 > > > - */ > > > - wa_write_or(wal, > > > - GEN9_CTX_PREEMPT_REG, > > > - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); > > > - } > > > - > > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || > > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { > > > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ > > > @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs > > > *engine, struct i915_wa_list *wal) > > > } > > > > > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || > > > - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || > > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { > > > - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ > > > + /* Wa_1409804808 */ > > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, > > > GEN12_PUSH_CONST_DEREF_HOLD_DIS); > > > > > > - /* > > > - * Wa_1409085225:tgl > > > - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p > > > - */ > > > + /* Wa_14010229206 */ > > > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, > > > GEN12_DISABLE_TDL_PUSH); > > > } > > > > > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || > > > - IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { > > > + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { > > > /* > > > - * Wa_1607030317:tgl > > > - * Wa_1607186500:tgl > > > - * Wa_1607297627:tgl,rkl,dg1[a0],adlp > > > + * Wa_1607297627 > > > * > > > * On TGL and RKL there are multiple entries for this WA in the > > > * BSpec; some indicate this is an A0-only WA, others indicate > > > * it applies to all steppings so we trust the "all steppings." > > > - * For DG1 this only applies to A0. > > > */ > > > wa_masked_en(wal, > > > RING_PSMI_CTL(RENDER_RING_BASE), > > > diff --git a/drivers/gpu/drm/i915/i915_driver.c > > > b/drivers/gpu/drm/i915/i915_driver.c > > > index 879ab4ed42af..397a2159fe12 100644 > > > --- a/drivers/gpu/drm/i915/i915_driver.c > > > +++ b/drivers/gpu/drm/i915/i915_driver.c > > > @@ -168,6 +168,7 @@ static void intel_detect_preproduction_hw(struct > > > drm_i915_private *dev_priv) > > > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; > > > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; > > > pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; > > > + pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; > > > > > > if (pre) { > > > drm_err(&dev_priv->drm, "This is a pre-production stepping. " > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > > b/drivers/gpu/drm/i915/i915_drv.h > > > index 62cc0f76c583..57b84dbca084 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -658,8 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > > > > > #define IS_DG1_GRAPHICS_STEP(p, since, until) \ > > > (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until)) > > > -#define IS_DG1_DISPLAY_STEP(p, since, until) \ > > > - (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until)) > > > > > > #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ > > > (IS_ALDERLAKE_S(__i915) && \ > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > > b/drivers/gpu/drm/i915/intel_pm.c > > > index c6676f1a9c6f..e0364c4141b8 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4353,15 +4353,6 @@ static void adlp_init_clock_gating(struct > > > drm_i915_private *dev_priv) > > > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); > > > } > > > > > > -static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) > > > -{ > > > - gen12lp_init_clock_gating(dev_priv); > > > - > > > - /* Wa_1409836686:dg1[a0] */ > > > - if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0)) > > > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, > > > DPT_GATING_DIS); > > > -} > > > - > > > static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv) > > > { > > > /* Wa_22010146351:xehpsdv */ > > > @@ -4781,7 +4772,6 @@ CG_FUNCS(pvc); > > > CG_FUNCS(dg2); > > > CG_FUNCS(xehpsdv); > > > CG_FUNCS(adlp); > > > -CG_FUNCS(dg1); > > > CG_FUNCS(gen12lp); > > > CG_FUNCS(icl); > > > CG_FUNCS(cfl); > > > @@ -4824,8 +4814,6 @@ void intel_init_clock_gating_hooks(struct > > > drm_i915_private *dev_priv) > > > dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs; > > > else if (IS_ALDERLAKE_P(dev_priv)) > > > dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs; > > > - else if (IS_DG1(dev_priv)) > > > - dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs; > > > > This will create warnings: > > > > MISSING_CASE down below... > > It shouldn't make it down that far since: > > > > else if (GRAPHICS_VER(dev_priv) == 12) > > will now match for DG1.
doh! indeed what we want... Reviewed-by: Rodrigo Vivi <[email protected]> > > > Matt > > > > dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs; > > > else if (GRAPHICS_VER(dev_priv) == 11) > > > -- > > > 2.39.1 > > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation
