On Wed, Jun 22, 2022 at 06:54:50PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > Like most other plane control register bits, the pipe gamma > enable bit is also blocked by CxSR. So make sure we kick the > machine out of CxSR before trying to change that bit. > > Signed-off-by: Ville Syrjälä <[email protected]>
Should that new i9xx_must_disable_cxsr function be extended to be used here as well? Besides that Reviewed-by: Stanislav Lisovskiy <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_color.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index a27ce874a9e8..bc01a7d3b0d3 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1305,6 +1305,10 @@ intel_color_add_affected_planes(struct > intel_crtc_state *new_crtc_state) > return PTR_ERR(plane_state); > > new_crtc_state->update_planes |= BIT(plane->id); > + > + /* plane control register changes blocked by CxSR */ > + if (HAS_GMCH(dev_priv)) > + new_crtc_state->disable_cxsr = true; > } > > return 0; > -- > 2.35.1 >
