On Tue, Sep 27, 2022 at 10:56:32AM -0700, Anusha Srivatsa wrote:
> From: Ville Syrjälä <[email protected]>
>
> For MTL, changing cdclk from between certain frequencies has
> both squash and crawl. Use the current cdclk config and
> the new(desired) cdclk config to construct a mid cdclk config.
> Set the cdclk twice:
> - Current cdclk -> mid cdclk
> - mid cdclk -> desired cdclk
I might have said we don't need any logic in intel_modeset_calc_cdclk()
but I didn't mean it entirely literally :) I think we do need a bit
of logic there to avoid taking the "force full modeset" path.
So some kind of
can_crawl_and_squash() {
return has_crawl && has_squash && old_vco != 0 && new_vco != 0;
}
should be sufficient I think.
Hmm, but I guess that would mean the debug message won't be 100%
accurate. So your idea of using the same logic from
cdclk_crawl_and_squash() here too might be the best option after
all.
>
> Signed-off-by: Anusha Srivatsa <[email protected]>
> Signed-off-by: Ville Syrjälä <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 121 ++++++++++++++++-----
> 1 file changed, 96 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a12e86d92783..e7faded38e66 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1689,37 +1689,70 @@ static u32 cdclk_squash_waveform(struct
> drm_i915_private *dev_priv,
> return 0xffff;
> }
>
> -static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> - const struct intel_cdclk_config *cdclk_config,
> - enum pipe pipe)
> +static int cdclk_squash_divider(u16 waveform)
> +{
> + return hweight16(waveform ?: 0xffff);
> +}
> +
> +static bool cdclk_crawl_and_squash(struct drm_i915_private *i915,
> + const struct intel_cdclk_config
> *old_cdclk_config,
> + const struct intel_cdclk_config
> *new_cdclk_config,
> + struct intel_cdclk_config *mid_cdclk_config)
> +{
> + u16 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
> + u16 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
> + u16 mid_waveform;
> + int size = 16;
> + int div = 2;
> +
> + if (!HAS_CDCLK_CRAWL(i915) || !has_cdclk_squasher(i915))
> + return false;
> +
> + /* Return if Squash only or Crawl only is the desired action */
> + if (old_cdclk_config->vco <= 0 || new_cdclk_config->vco <= 0 ||
> + old_cdclk_config->vco == new_cdclk_config->vco ||
> + old_waveform == new_waveform)
> + return false;
> +
> + *mid_cdclk_config = *new_cdclk_config;
> +
> + /* If moving to a higher cdclk(squash) the mid cdclk config
> + * should have the new (squash) waveform.
> + * If moving to a lower cdclk (crawl) the mid cdclk config
> + * should have the new vco.
> + */
> +
> + if (cdclk_squash_divider(new_waveform) >
> cdclk_squash_divider(old_waveform)) {
> + mid_cdclk_config->vco = old_cdclk_config->vco;
> + mid_waveform = new_waveform;
> + } else {
> + mid_cdclk_config->vco = new_cdclk_config->vco;
> + mid_waveform = old_waveform;
> + }
> +
> + mid_cdclk_config->cdclk =
> DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
> + mid_cdclk_config->vco, size
> * div);
> +
> + /* make sure the mid clock came out sane */
> + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
> + min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
> + drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
> + i915->display.cdclk.max_cdclk_freq);
> + drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915,
> mid_cdclk_config->cdclk) !=
> + mid_waveform);
> +
> + return true;
> +}
> +
> +static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *cdclk_config,
> + enum pipe pipe)
> {
> int cdclk = cdclk_config->cdclk;
> int vco = cdclk_config->vco;
> u32 val;
> u16 waveform;
> int clock;
> - int ret;
> -
> - /* Inform power controller of upcoming frequency change. */
> - if (DISPLAY_VER(dev_priv) >= 11)
> - ret = skl_pcode_request(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> - else
> - /*
> - * BSpec requires us to wait up to 150usec, but that leads to
> - * timeouts; the 2ms used here is based on experiment.
> - */
> - ret = snb_pcode_write_timeout(&dev_priv->uncore,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - 0x80000000, 150, 2);
> - if (ret) {
> - drm_err(&dev_priv->drm,
> - "Failed to inform PCU about cdclk change (err %d, freq
> %d)\n",
> - ret, cdclk);
> - return;
> - }
>
> if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 &&
> vco > 0) {
> if (dev_priv->display.cdclk.hw.vco != vco)
> @@ -1772,6 +1805,44 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
>
> if (pipe != INVALID_PIPE)
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
> pipe));
> +}
> +
> +static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> + const struct intel_cdclk_config *cdclk_config,
> + enum pipe pipe)
> +{
> + struct intel_cdclk_config mid_cdclk_config;
> + int cdclk = cdclk_config->cdclk;
> + int ret;
> +
> + /* Inform power controller of upcoming frequency change. */
> + if (DISPLAY_VER(dev_priv) >= 11)
> + ret = skl_pcode_request(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + else
> + /*
> + * BSpec requires us to wait up to 150usec, but that leads to
> + * timeouts; the 2ms used here is based on experiment.
> + */
> + ret = snb_pcode_write_timeout(&dev_priv->uncore,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + 0x80000000, 150, 2);
> + if (ret) {
> + drm_err(&dev_priv->drm,
> + "Failed to inform PCU about cdclk change (err %d, freq
> %d)\n",
> + ret, cdclk);
> + return;
> + }
> +
> + if (cdclk_crawl_and_squash(dev_priv, &dev_priv->display.cdclk.hw,
> + cdclk_config, &mid_cdclk_config)) {
> + _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
> + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + } else {
> + _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
> + }
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> ret = snb_pcode_write(&dev_priv->uncore,
> SKL_PCODE_CDCLK_CONTROL,
> --
> 2.25.1
--
Ville Syrjälä
Intel
