From: Ville Syrjälä <[email protected]> When using local memory, we need to encode the PTEs correctly. Since cache_mode is the only thing that gets passed down there, add a new cache_level that's only used for objects allocated from local memory.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++- drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +++++++++++++--- 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 20a9811..9ee725f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -515,6 +515,7 @@ enum i915_cache_level { large Last-Level-Cache. LLC is coherent with the CPU, but L3 is only visible to the GPU. */ I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ + I915_CACHE_LOCAL, /* local memory */ }; typedef uint32_t gen6_gtt_pte_t; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1bd8953..b08d5d3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1392,7 +1392,8 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) trace_i915_gem_object_fault(obj, page_offset, true, write); /* Access to snoopable pages through the GTT is incoherent. */ - if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { + if (obj->cache_level != I915_CACHE_NONE && + obj->cache_level != I915_CACHE_LOCAL && !HAS_LLC(dev)) { ret = -EINVAL; goto unlock; } @@ -3478,6 +3479,13 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (obj->cache_level == cache_level) return 0; + if (obj->cache_level == I915_CACHE_LOCAL) { + if (cache_level != I915_CACHE_NONE) + return -EINVAL; + + return 0; + } + if (obj->pin_count) { DRM_DEBUG("can not change the cache level of pinned objects\n"); return -EBUSY; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 70b148c..0eb6203 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1022,11 +1022,21 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm, unsigned int pg_start, enum i915_cache_level cache_level) { - unsigned int flags = (cache_level == I915_CACHE_NONE) ? - AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; + unsigned int flags; - intel_gtt_insert_sg_entries(st, pg_start, flags); + switch (cache_level) { + case I915_CACHE_NONE: + flags = AGP_USER_MEMORY; + break; + case I915_CACHE_LOCAL: + flags = AGP_DCACHE_MEMORY; + break; + default: + flags = AGP_USER_CACHED_MEMORY; + break; + } + intel_gtt_insert_sg_entries(st, pg_start, flags); } static void i915_ggtt_clear_range(struct i915_address_space *vm, -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
