On Wed, 17 Aug 2022, "Kahola, Mika" <[email protected]> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <[email protected]>
>> Sent: Wednesday, August 17, 2022 3:26 PM
>> To: [email protected]
>> Cc: Nikula, Jani <[email protected]>; Ville Syrjälä
>> <[email protected]>; Kahola, Mika <[email protected]>
>> Subject: [PATCH] drm/i915/mtl: Introduce FBC B
>>
>> From: Ville Syrjälä <[email protected]>
>>
>> MTL introduces a second FBC engine. The two FBC engines can operate entirely
>> independently, FBC A serving pipe A and FBC B serving pipe B.
>>
>> The one place where things might go a bit wrong is the CFB allocation from
>> stolen. We might have to consider some change to the allocation strategy to
>> have a better chance of both engines being able to allocate its CFB. Maybe
>> FBC
>> A should allocate bottom up and FBC B top down, or something? For the
>> moment the allocation strategy is DRM_MM_INSERT_BEST for both.
>>
>> Cc: Mika Kahola <[email protected]>
>> Signed-off-by: Ville Syrjälä <[email protected]>
>> Signed-off-by: Jani Nikula <[email protected]>
>
> Reviewed-by: Mika Kahola <[email protected]>
Thanks for the review, pushed to drm-intel-next.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_fbc.h | 1 +
>> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
>> b/drivers/gpu/drm/i915/display/intel_fbc.h
>> index db60143295ec..4adb98afe6ff 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
>> @@ -19,6 +19,7 @@ struct intel_plane_state;
>>
>> enum intel_fbc_id {
>> INTEL_FBC_A,
>> + INTEL_FBC_B,
>>
>> I915_MAX_FBCS,
>> };
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index 9fd788e147a3..d8446bb25d5e 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -1111,7 +1111,8 @@ static const struct intel_device_info pvc_info = {
>> #define XE_LPDP_FEATURES \
>> XE_LPD_FEATURES, \
>> .display.ver = 14, \
>> - .display.has_cdclk_crawl = 1
>> + .display.has_cdclk_crawl = 1, \
>> + .display.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
>>
>> __maybe_unused
>> static const struct intel_device_info mtl_info = {
>> --
>> 2.34.1
>
--
Jani Nikula, Intel Open Source Graphics Center
