On Tue, 15 Feb 2022, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Let's not replicate the same piece of code to expand > the MSO segment timings to full width in many places. > Pull it into a helper
Did I duplicate that? Yuck. Reviewed-by: Jani Nikula <[email protected]> > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 54 ++++++++++---------- > 1 file changed, 26 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 5da8db3dda8f..70017526fa81 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2724,6 +2724,30 @@ static void intel_crtc_compute_pixel_rate(struct > intel_crtc_state *crtc_state) > ilk_pipe_pixel_rate(crtc_state); > } > > +static void intel_splitter_adjust_timings(const struct intel_crtc_state > *crtc_state, > + struct drm_display_mode *mode) > +{ > + int overlap = crtc_state->splitter.pixel_overlap; > + int n = crtc_state->splitter.link_count; > + > + if (!crtc_state->splitter.enable) > + return; > + > + /* > + * eDP MSO uses segment timings from EDID for transcoder > + * timings, but full mode for everything else. > + * > + * h_full = (h_segment - pixel_overlap) * link_count > + */ > + mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; > + mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; > + mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; > + mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; > + mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; > + mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; > + mode->crtc_clock *= n; > +} > + > static void intel_crtc_readout_derived_state(struct intel_crtc_state > *crtc_state) > { > struct drm_display_mode *mode = &crtc_state->hw.mode; > @@ -2747,22 +2771,7 @@ static void intel_crtc_readout_derived_state(struct > intel_crtc_state *crtc_state > } > > if (crtc_state->splitter.enable) { > - int n = crtc_state->splitter.link_count; > - int overlap = crtc_state->splitter.pixel_overlap; > - > - /* > - * eDP MSO uses segment timings from EDID for transcoder > - * timings, but full mode for everything else. > - * > - * h_full = (h_segment - pixel_overlap) * link_count > - */ > - pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) > * n; > - pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - > overlap) * n; > - pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - > overlap) * n; > - pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - > overlap) * n; > - pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - > overlap) * n; > - pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n; > - pipe_mode->crtc_clock *= n; > + intel_splitter_adjust_timings(crtc_state, pipe_mode); > > intel_mode_from_crtc_timings(pipe_mode, pipe_mode); > intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); > @@ -2807,18 +2816,7 @@ static int intel_crtc_compute_config(struct intel_crtc > *crtc, > crtc_state->pipe_src_w /= 2; > } > > - if (crtc_state->splitter.enable) { > - int n = crtc_state->splitter.link_count; > - int overlap = crtc_state->splitter.pixel_overlap; > - > - pipe_mode->crtc_hdisplay = (pipe_mode->crtc_hdisplay - overlap) > * n; > - pipe_mode->crtc_hblank_start = (pipe_mode->crtc_hblank_start - > overlap) * n; > - pipe_mode->crtc_hblank_end = (pipe_mode->crtc_hblank_end - > overlap) * n; > - pipe_mode->crtc_hsync_start = (pipe_mode->crtc_hsync_start - > overlap) * n; > - pipe_mode->crtc_hsync_end = (pipe_mode->crtc_hsync_end - > overlap) * n; > - pipe_mode->crtc_htotal = (pipe_mode->crtc_htotal - overlap) * n; > - pipe_mode->crtc_clock *= n; > - } > + intel_splitter_adjust_timings(crtc_state, pipe_mode); > > intel_mode_from_crtc_timings(pipe_mode, pipe_mode); -- Jani Nikula, Intel Open Source Graphics Center
