From: Ville Syrjälä <[email protected]> Just use a same mask for ivb/hsw as for bdw+. The extra bit in the bdw mask is mbz on ivb/hsw anyway so this is just pointless complexity.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_fbc.c | 5 +---- drivers/gpu/drm/i915/i915_reg.h | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index b13a776cb3dc..1193e86690e5 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -533,10 +533,7 @@ static void ivb_fbc_activate(struct drm_i915_private *dev_priv) static bool ivb_fbc_is_compressing(struct drm_i915_private *i915) { - if (DISPLAY_VER(i915) >= 8) - return intel_de_read(i915, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; - else - return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; + return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; } static void ivb_fbc_set_false_color(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b456920555b7..1e99fe8dc253 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3382,8 +3382,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ILK_DPFC_STATUS _MMIO(0x43210) #define ILK_DPFC_COMP_SEG_MASK 0x7ff #define IVB_FBC_STATUS2 _MMIO(0x43214) -#define IVB_FBC_COMP_SEG_MASK 0x7ff -#define BDW_FBC_COMP_SEG_MASK 0xfff +#define IVB_FBC_COMP_SEG_MASK 0xfff #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) #define ILK_DPFC_CHICKEN _MMIO(0x43224) #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) -- 2.32.0
