On Fri, 4 Oct 2013 20:32:25 +0300 [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > The VGACNTRL register contains a bunch of other stuff besides > the VGA_DISP_DISABLE bit. When we write the register we always set those > other bits to zero, so normally the current check would work. > > However on HSW disabling and re-enabling the power well will reset the > VGACNTRL register to its default value, which has several of the other > bits set as well. > > So only look at the VGA_DISP_DISABLE bit when checking whether the VGA > plane needs re-disabling. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 0ba0af4..925a387 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10659,7 +10659,7 @@ void i915_redisable_vga(struct drm_device *dev) > (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) > return; > > - if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { > + if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { > DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); > i915_disable_vga(dev); > i915_disable_vga_mem(dev);
Looks good. Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
