On Tue, Oct 01, 2013 at 02:54:26PM -0700, Jesse Barnes wrote: > On Wed, 25 Sep 2013 17:34:56 +0100 > Chris Wilson <[email protected]> wrote: > > > +void gen6_rps_idle(struct drm_i915_private *dev_priv) > > +{ > > + mutex_lock(&dev_priv->rps.hw_lock); > > + if (dev_priv->info->is_valleyview) > > + valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > > + else > > + gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); > > + mutex_unlock(&dev_priv->rps.hw_lock); > > +} > > Looks pretty good, but I think these should be rpe_delay instead. Not > much point in going down to a less efficient frequency...
Less efficient for what? My concern here is only with power draw when idle. As soon as we start to render again (well very shortly afterwards with this particular iteration) we bump up to rpe and then beyond. Correct me if I am wrong but rpe is an inflection point rather than a minumum? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
