== Series Details == Series: series starting with [1/2] drm/i915/display/adl_p: Implement PSR changes URL : https://patchwork.freedesktop.org/series/91931/ State : warning
== Summary == $ dim checkpatch origin/drm-tip 40703d3f9d23 drm/i915/display/adl_p: Implement PSR changes -:149: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #149: FILE: drivers/gpu/drm/i915/i915_reg.h:4660: +#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) -:152: WARNING:LONG_LINE: line length of 127 exceeds 100 columns #152: FILE: drivers/gpu/drm/i915/i915_reg.h:4663: +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) -:162: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #162: FILE: drivers/gpu/drm/i915/i915_reg.h:4670: +#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) -:164: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #164: FILE: drivers/gpu/drm/i915/i915_reg.h:4672: +#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) total: 0 errors, 4 warnings, 0 checks, 131 lines checked 399cecf3f729 drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
