Hi upstream committee, Please consider to merge this patch which resolved VP8 hardware encoding GPU hang critical issue on Gen9 sku and there is no any performance regression on this fix. Meanwhile it's critical for Chrome projects need your help to review to merge it. Thanks,
Best Regards, Cooper -----Original Message----- From: Chiou, Cooper <[email protected]> Sent: Thursday, September 17, 2020 2:08 AM To: [email protected] Cc: Chiou, Cooper <[email protected]>; Ville Syrjälä <[email protected]>; Vivi, Rodrigo <[email protected]>; Nikula, Jani <[email protected]>; Chris Wilson <[email protected]>; Tvrtko Ursulin <[email protected]>; Tseng, William <[email protected]>; Lee, Shawn C <[email protected]> Subject: [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8 hardware encoding system hang up on GT1 sku Reference: HSD#1508045018 Cc: Ville Syrjälä <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: William Tseng <[email protected]> Cc: Lee Shawn C <[email protected]> Signed-off-by: Cooper Chiou <[email protected]> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5726cd0a37e0..53ea4359545b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -935,9 +935,13 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); } +static void wa_init_mcr(struct drm_i915_private *i915, struct +i915_wa_list *wal); + static void gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { + wa_init_mcr(i915, wal); + /* WaDisableKillLogic:bxt,skl,kbl */ if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) wa_write_or(wal, @@ -1040,7 +1044,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) unsigned int slice, subslice; u32 l3_en, mcr, mcr_mask; - GEM_BUG_ON(INTEL_GEN(i915) < 10); + GEM_BUG_ON(INTEL_GEN(i915) < 9); /* * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl @@ -1049,7 +1053,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) * by default, to make sure we correctly read certain registers * later on (in the range 0xB100 - 0xB3FF). * - * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl + * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,cnl,icl * Before any MMIO read into slice/subslice specific registers, MCR * packet control register needs to be programmed to point to any * enabled s/ss pair. Otherwise, incorrect values will be returned. -- 2.28.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
