Chris Wilson <[email protected]> writes: > The surface_state_base is an offset into the batch, so we need to pass > the correct batch address for STATE_BASE_ADDRESS. > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > Cc: Prathap Kumar Valsan <[email protected]> > Cc: Akeem G Abodunrin <[email protected]>
Reviewed-by: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > index e403eb046a43..de575fdb033f 100644 > --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c > @@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch, > /* general */ > *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; > /* surface */ > - *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY; > + *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; > /* dynamic */ > *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; > /* indirect */ > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
