From: Ville Syrjälä <[email protected]> Extract some helpers to calculate the correct CLK_SEL values for DPCLKA_CFGCR.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++++++++++++--------- 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a3aeb1c2821c..23fbb9013e09 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3127,6 +3127,28 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, return 0; } +static u32 icl_dpclka_cfgcr0_clk_sel(struct drm_i915_private *dev_priv, + enum intel_dpll_id id, enum phy phy) +{ + if (IS_ALDERLAKE_S(dev_priv)) + return id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy); + else if (IS_ROCKETLAKE(dev_priv)) + return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy); + else + return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(id, phy); +} + +static u32 icl_dpclka_cfgcr0_clk_sel_mask(struct drm_i915_private *dev_priv, + enum phy phy) +{ + if (IS_ALDERLAKE_S(dev_priv)) + return ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); + else if (IS_ROCKETLAKE(dev_priv)) + return RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + else + return ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); +} + static i915_reg_t icl_dpclka_cfgcr0_reg(struct drm_i915_private *i915, enum phy phy) { @@ -3177,18 +3199,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy); - u32 val, mask, sel; - - if (IS_ALDERLAKE_S(dev_priv)) { - mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); - sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); - } else if (IS_ROCKETLAKE(dev_priv)) { - mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } else { - mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } + u32 val; mutex_lock(&dev_priv->dpll.lock); @@ -3207,8 +3218,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~mask; - val |= sel; + val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy); + val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy); intel_de_write(dev_priv, reg, val); intel_de_posting_read(dev_priv, reg); } -- 2.26.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
