> -----Original Message-----
> From: Chris Wilson <[email protected]>
> Sent: Sunday, January 17, 2021 1:30 AM
> To: [email protected]
> Cc: Chris Wilson <[email protected]>; Mika Kuoppala
> <[email protected]>; Abodunrin, Akeem G
> <[email protected]>
> Subject: [PATCH] drm/i915/gt: Clear CACHE_MODE prior to clearing residuals
>
> Since we do a bare context switch with no restore, the clear residual kernel
> runs on dirty state, and we must be careful to avoid executing bad state from
> context registers inherited from a malicious client.
>
> Fixes: 008ead6ef8f5 ("drm/i915/gt: Restore clear-residual mitigations for
> Ivybridge, Baytrail")
> Fixes: 09aa9e45863e ("drm/i915/gt: Restore clear-residual mitigations for
> Ivybridge, Baytrail")
> Testcase: igt/gem_ctx_isolation # ivb,vlv
> Signed-off-by: Chris Wilson <[email protected]>
> Cc: Mika Kuoppala <[email protected]>
> Cc: Akeem G Abodunrin <[email protected]>
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index 56bdcdaa9a88..0490c29788d7 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -390,6 +390,14 @@ static void emit_batch(struct i915_vma * const
> vma,
> &cb_kernel_ivb,
> desc_count);
>
> + gen7_emit_pipeline_invalidate(&cmds);
> + batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
> + batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
> + batch_add(&cmds, 0xffff0000);
> + batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
> + batch_add(&cmds, 0xffff0000 |
> PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
> + gen7_emit_pipeline_flush(&cmds);
> +
> gen7_emit_pipeline_invalidate(&cmds);
> batch_add(&cmds, PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
> batch_add(&cmds, MI_NOOP);
> --
> 2.20.1
Reviewed-by: Akeem G Abodunrin <[email protected]>
Thanks,
~Akeem
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