On Thu, Dec 10, 2020 at 08:02:40AM +0000, Chris Wilson wrote: > When we are not using semaphores with a context/engine, we can simply > reuse the same seqno location across wraps, but we still require each > timeline to have its own address. For LRC submission, each context is > prefixed by a per-process HWSP, which provides us with a unique location > for each context-local timeline. A shared timeline that is common to > multiple contexts will continue to use a separate page. > > This enables us to create position invariant contexts should we feel the > need to relocate them. >
Reviewed-by: Matthew Brost <[email protected]> > Signed-off-by: Chris Wilson <[email protected]> > Cc: Joonas Lahtinen <[email protected]> > --- > .../drm/i915/gt/intel_execlists_submission.c | 37 +++++++++++-------- > 1 file changed, 22 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 8bff0559a6a9..cc1b3509d808 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -4749,6 +4749,14 @@ static struct intel_timeline *pinned_timeline(struct > intel_context *ce) > page_unmask_bits(tl)); > } > > +static struct intel_timeline *pphwsp_timeline(struct intel_context *ce, > + struct i915_vma *state) > +{ > + return __intel_timeline_create(ce->engine->gt, state, > + I915_GEM_HWS_SEQNO_ADDR | > + INTEL_TIMELINE_CONTEXT); > +} > + > static int __execlists_context_alloc(struct intel_context *ce, > struct intel_engine_cs *engine) > { > @@ -4779,6 +4787,16 @@ static int __execlists_context_alloc(struct > intel_context *ce, > goto error_deref_obj; > } > > + ring = intel_engine_create_ring(engine, (unsigned long)ce->ring); > + if (IS_ERR(ring)) { > + ret = PTR_ERR(ring); > + goto error_deref_obj; > + } > + > + ret = populate_lr_context(ce, ctx_obj, engine, ring); > + if (ret) > + goto error_ring_free; > + > if (!page_mask_bits(ce->timeline)) { > struct intel_timeline *tl; > > @@ -4788,29 +4806,18 @@ static int __execlists_context_alloc(struct > intel_context *ce, > */ > if (unlikely(ce->timeline)) > tl = pinned_timeline(ce); > - else > + else if (intel_engine_has_semaphores(engine)) > tl = intel_timeline_create(engine->gt); > + else > + tl = pphwsp_timeline(ce, vma); > if (IS_ERR(tl)) { > ret = PTR_ERR(tl); > - goto error_deref_obj; > + goto error_ring_free; > } > > ce->timeline = tl; > } > > - ring = intel_engine_create_ring(engine, (unsigned long)ce->ring); > - if (IS_ERR(ring)) { > - ret = PTR_ERR(ring); > - goto error_deref_obj; > - } > - > - ret = populate_lr_context(ce, ctx_obj, engine, ring); > - if (ret) { > - drm_dbg(&engine->i915->drm, > - "Failed to populate LRC: %d\n", ret); > - goto error_ring_free; > - } > - > ce->ring = ring; > ce->state = vma; > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
