> -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Ville > Syrjala > Sent: Friday, September 18, 2020 3:14 AM > To: [email protected] > Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Decouple intel_dp_{min, > output}_bpp() from crtc_state > > From: Ville Syrjälä <[email protected]> > > Pass the output_format directly to intel_dp_{min,output}_bpp() rather than > passing in the crtc_state and digging out the output_format inside the > functions. This will allow us to reuse the functions for mode validation > purposes. > > Signed-off-by: Ville Syrjälä <[email protected]>
Looks good to me. Reviewed-by: Vandita Kulkarni <[email protected]> Thanks, Vandita > --- > drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++------- > drivers/gpu/drm/i915/display/intel_dp.h | 3 ++- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > 3 files changed, 11 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index ad9b8b16fadb..aa4801a8123d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2111,14 +2111,14 @@ intel_dp_adjust_compliance_config(struct > intel_dp *intel_dp, > } > } > > -static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int > bpp) > +static int intel_dp_output_bpp(enum intel_output_format output_format, > +int bpp) > { > /* > * bpp value was assumed to RGB format. And YCbCr 4:2:0 output > * format of the number of bytes per pixel will be half the number > * of bytes of RGB pixel. > */ > - if (crtc_state->output_format == > INTEL_OUTPUT_FORMAT_YCBCR420) > + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) > bpp /= 2; > > return bpp; > @@ -2135,7 +2135,7 @@ intel_dp_compute_link_config_wide(struct > intel_dp *intel_dp, > int mode_rate, link_clock, link_avail; > > for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { > - int output_bpp = intel_dp_output_bpp(pipe_config, bpp); > + int output_bpp = intel_dp_output_bpp(pipe_config- > >output_format, > +bpp); > > mode_rate = intel_dp_link_required(adjusted_mode- > >crtc_clock, > output_bpp); > @@ -2346,9 +2346,9 @@ static int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > return 0; > } > > -int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) > +int intel_dp_min_bpp(enum intel_output_format output_format) > { > - if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) > + if (output_format == INTEL_OUTPUT_FORMAT_RGB) > return 6 * 3; > else > return 8 * 3; > @@ -2379,7 +2379,7 @@ intel_dp_compute_link_config(struct > intel_encoder *encoder, > limits.min_lane_count = 1; > limits.max_lane_count = intel_dp_max_lane_count(intel_dp); > > - limits.min_bpp = intel_dp_min_bpp(pipe_config); > + limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); > limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); > > if (intel_dp_is_edp(intel_dp)) { > @@ -2765,7 +2765,8 @@ intel_dp_compute_config(struct intel_encoder > *encoder, > if (pipe_config->dsc.compression_enable) > output_bpp = pipe_config->dsc.compressed_bpp; > else > - output_bpp = intel_dp_output_bpp(pipe_config, > pipe_config->pipe_bpp); > + output_bpp = intel_dp_output_bpp(pipe_config- > >output_format, > + pipe_config->pipe_bpp); > > intel_link_compute_m_n(output_bpp, > pipe_config->lane_count, > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index 08a1c0aa8b94..a9580d1df35b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -10,6 +10,7 @@ > > #include "i915_reg.h" > > +enum intel_output_format; > enum pipe; > enum port; > struct drm_connector_state; > @@ -35,7 +36,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp > *intel_dp, > struct link_config_limits *limits); bool > intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, > const struct drm_connector_state > *conn_state); -int intel_dp_min_bpp(const struct intel_crtc_state > *crtc_state); > +int intel_dp_min_bpp(enum intel_output_format output_format); > bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, > i915_reg_t dp_reg, enum port port, > enum pipe *pipe); > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 64d885539e94..6a874b779b1f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -130,7 +130,7 @@ static int intel_dp_mst_compute_config(struct > intel_encoder *encoder, > limits.min_lane_count = > limits.max_lane_count = intel_dp_max_lane_count(intel_dp); > > - limits.min_bpp = intel_dp_min_bpp(pipe_config); > + limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); > /* > * FIXME: If all the streams can't fit into the link with > * their current pipe_bpp we should reduce pipe_bpp across > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
