From: Venkata Sandeep Dhanalakota <[email protected]> On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Michael J. Ruhl <[email protected]> Signed-off-by: Venkata Sandeep Dhanalakota <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> --- drivers/gpu/drm/i915/intel_uncore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 592364aed2da..49d2cfb55bb2 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1699,11 +1699,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore) * clobbering the GTT which we want ioremap_wc instead. Fortunately, * the register BAR remains the same size for all the earlier * generations up to Ironlake. + * For dgfx chips register range is expanded to 4MB. */ if (INTEL_GEN(i915) < 5) mmio_size = 512 * 1024; + else if (IS_DGFX(i915)) + mmio_size = 4 * 1024 * 1024; else mmio_size = 2 * 1024 * 1024; + uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); if (uncore->regs == NULL) { drm_err(&i915->drm, "failed to map registers\n"); -- 2.26.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
