This WA fixes failures on DP and HDMI links in PHY B. For the PHY verification step, it is always returning false as this is a temporary workaround so not bothering with minimal drawbacks in programing phy B registers everytime for non-production HW.
BSpec: 49291 BSpec: 53273 Cc: Matt Roper <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> --- .../gpu/drm/i915/display/intel_combo_phy.c | 33 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..9eba6e59fff3 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -264,6 +264,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, if (!icl_combo_phy_enabled(dev_priv, phy)) return false; + /* WA 14011471926 */ + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B) + return false; + ret = cnl_verify_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { @@ -390,6 +394,35 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); + + /* WA 14011471926 */ + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && + phy == PHY_B) { + u32 grccode; + + intel_de_wait_for_register(dev_priv, + ICL_PORT_COMP_DW3(PHY_A), + FIRST_COMP_DONE, + FIRST_COMP_DONE, 1); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW6(PHY_A)); + grccode = REG_FIELD_GET(ICL_PORT_COMP_DW6_GRCCODE_MASK, val); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW2(phy)); + val &= ~ICL_PORT_COMP_DW2_IREF_RCAL_ORD_MASK; + val |= REG_FIELD_PREP(ICL_PORT_COMP_DW2_IREF_RCAL_ORD_MASK, grccode); + val |= ICL_PORT_COMP_DW2_IREF_RCAL_ORD_END; + intel_de_write(dev_priv, ICL_PORT_COMP_DW2(phy), val); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(PHY_A)); + grccode = REG_FIELD_GET(ICL_PORT_COMP_DW0_GRCCODE_LDO_MASK, val); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW6(phy)); + val &= ~ICL_PORT_COMP_DW6_RCOMPCODE_LD_CAP_OV_MASK; + val |= REG_FIELD_PREP(ICL_PORT_COMP_DW6_RCOMPCODE_LD_CAP_OV_MASK, grccode); + val |= ICL_PORT_COMP_DW6_RCOMPCODEOVEN_LDO_SYNC; + intel_de_write(dev_priv, ICL_PORT_COMP_DW6(phy), val); + } } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..dbbe20a38345 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1907,13 +1907,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_COMP + 4 * (dw)) -#define CNL_PORT_COMP_DW0 _MMIO(0x162100) -#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT (1 << 31) +#define CNL_PORT_COMP_DW0 _MMIO(0x162100) +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) +#define COMP_INIT REG_BIT(31) +#define ICL_PORT_COMP_DW0_GRCCODE_LDO_MASK REG_GENMASK(7, 0) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) +#define ICL_PORT_COMP_DW2_IREF_RCAL_ORD_END REG_BIT(7) +#define ICL_PORT_COMP_DW2_IREF_RCAL_ORD_MASK REG_GENMASK(6, 0) + #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) @@ -1926,6 +1931,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VOLTAGE_INFO_1_05V (2 << 24) #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 +#define FIRST_COMP_DONE (1 << 22) + +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) +#define ICL_PORT_COMP_DW6_GRCCODE_MASK REG_GENMASK(30, 24) +#define ICL_PORT_COMP_DW6_RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) +#define ICL_PORT_COMP_DW6_RCOMPCODE_LD_CAP_OV_MASK REG_GENMASK(22, 16) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) -- 2.27.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
