On Wed, Feb 05, 2020 at 06:08:50PM -0800, José Roberto de Souza wrote: > From: Radhakrishna Sripada <[email protected]> > > Platforms without fences don't have FBC host tracking and those > registers are marked as reserved in those platforms. > > v2: checking num_fences to write to FBC fence registers (Ville) > > Cc: Rodrigo Vivi <[email protected]> > Cc: Matt Roper <[email protected]> > Cc: Dhinakaran Pandiyan <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Radhakrishna Sripada <[email protected]> > Signed-off-by: Lucas De Marchi <[email protected]> > Signed-off-by: José Roberto de Souza <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index 3a9e41e93ebf..fa8fca1a6b7c 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -320,7 +320,7 @@ static void gen7_fbc_activate(struct drm_i915_private > *dev_priv) > SNB_CPU_FENCE_ENABLE | params->fence_id); > intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, > params->crtc.fence_y_offset); > - } else { > + } else if (dev_priv->ggtt.num_fences) { > intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); > intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); > } > -- > 2.25.0 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
