On Tue, Oct 22, 2019 at 04:34:13PM +0300, Jani Nikula wrote: > Reduce verbosity in code by renaming dsc_params member of crtc state to > simply dsc. There is enough context for this to be clear. No functional > changes.
Makes sense to just call it dsc Reviewed-by: Manasi Navare <[email protected]> Manasi > > Cc: Manasi Navare <[email protected]> > Signed-off-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > .../drm/i915/display/intel_display_types.h | 2 +- > drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++----- > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > drivers/gpu/drm/i915/display/intel_vdsc.c | 68 +++++++++---------- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > 6 files changed, 55 insertions(+), 55 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 9ba794cb9b4f..1a49266f4f57 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2234,7 +2234,7 @@ static void intel_ddi_get_power_domains(struct > intel_encoder *encoder, > /* > * VDSC power is needed when DSC is enabled > */ > - if (crtc_state->dsc_params.compression_enable) > + if (crtc_state->dsc.compression_enable) > intel_display_power_get(dev_priv, > intel_dsc_power_domain(crtc_state)); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8358152e403e..db66f9d623f8 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -986,7 +986,7 @@ struct intel_crtc_state { > bool dsc_split; > u16 compressed_bpp; > u8 slice_count; > - } dsc_params; > + } dsc; > struct drm_dsc_config dp_dsc_cfg; > > /* Forward Error correction State */ > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 5eeafa45831a..521ce23f38ac 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2080,10 +2080,10 @@ static int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > pipe_config->lane_count = limits->max_lane_count; > > if (intel_dp_is_edp(intel_dp)) { > - pipe_config->dsc_params.compressed_bpp = > + pipe_config->dsc.compressed_bpp = > min_t(u16, > drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, > pipe_config->pipe_bpp); > - pipe_config->dsc_params.slice_count = > + pipe_config->dsc.slice_count = > drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, > true); > } else { > @@ -2104,10 +2104,10 @@ static int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > DRM_DEBUG_KMS("Compressed BPP/Slice Count not > supported\n"); > return -EINVAL; > } > - pipe_config->dsc_params.compressed_bpp = min_t(u16, > + pipe_config->dsc.compressed_bpp = min_t(u16, > > dsc_max_output_bpp >> 4, > > pipe_config->pipe_bpp); > - pipe_config->dsc_params.slice_count = dsc_dp_slice_count; > + pipe_config->dsc.slice_count = dsc_dp_slice_count; > } > /* > * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate > @@ -2115,8 +2115,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp > *intel_dp, > * then we need to use 2 VDSC instances. > */ > if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { > - if (pipe_config->dsc_params.slice_count > 1) { > - pipe_config->dsc_params.dsc_split = true; > + if (pipe_config->dsc.slice_count > 1) { > + pipe_config->dsc.dsc_split = true; > } else { > DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC > instances\n"); > return -EINVAL; > @@ -2128,16 +2128,16 @@ static int intel_dp_dsc_compute_config(struct > intel_dp *intel_dp, > DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input > Bpp = %d " > "Compressed BPP = %d\n", > pipe_config->pipe_bpp, > - pipe_config->dsc_params.compressed_bpp); > + pipe_config->dsc.compressed_bpp); > return ret; > } > > - pipe_config->dsc_params.compression_enable = true; > + pipe_config->dsc.compression_enable = true; > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " > "Compressed Bpp = %d Slice Count = %d\n", > pipe_config->pipe_bpp, > - pipe_config->dsc_params.compressed_bpp, > - pipe_config->dsc_params.slice_count); > + pipe_config->dsc.compressed_bpp, > + pipe_config->dsc.slice_count); > > return 0; > } > @@ -2211,15 +2211,15 @@ intel_dp_compute_link_config(struct intel_encoder > *encoder, > return ret; > } > > - if (pipe_config->dsc_params.compression_enable) { > + if (pipe_config->dsc.compression_enable) { > DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d > Compressed bpp %d\n", > pipe_config->lane_count, pipe_config->port_clock, > pipe_config->pipe_bpp, > - pipe_config->dsc_params.compressed_bpp); > + pipe_config->dsc.compressed_bpp); > > DRM_DEBUG_KMS("DP link rate required %i available %i\n", > intel_dp_link_required(adjusted_mode->crtc_clock, > - > pipe_config->dsc_params.compressed_bpp), > + > pipe_config->dsc.compressed_bpp), > intel_dp_max_data_rate(pipe_config->port_clock, > pipe_config->lane_count)); > } else { > @@ -2377,8 +2377,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, > pipe_config->limited_color_range = > intel_dp_limited_color_range(pipe_config, conn_state); > > - if (pipe_config->dsc_params.compression_enable) > - output_bpp = pipe_config->dsc_params.compressed_bpp; > + if (pipe_config->dsc.compression_enable) > + output_bpp = pipe_config->dsc.compressed_bpp; > else > output_bpp = intel_dp_output_bpp(pipe_config, > pipe_config->pipe_bpp); > > @@ -3102,7 +3102,7 @@ void intel_dp_sink_set_decompression_state(struct > intel_dp *intel_dp, > { > int ret; > > - if (!crtc_state->dsc_params.compression_enable) > + if (!crtc_state->dsc.compression_enable) > return; > > ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 50f22abcd30e..dfbedff98ea8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -76,7 +76,7 @@ static bool intel_psr2_enabled(struct drm_i915_private > *dev_priv, > const struct intel_crtc_state *crtc_state) > { > /* Cannot enable DSC and PSR2 simultaneously */ > - WARN_ON(crtc_state->dsc_params.compression_enable && > + WARN_ON(crtc_state->dsc.compression_enable && > crtc_state->has_psr2); > > switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { > @@ -623,7 +623,7 @@ static bool intel_psr2_config_valid(struct intel_dp > *intel_dp, > * resolution requires DSC to be enabled, priority is given to DSC > * over PSR2. > */ > - if (crtc_state->dsc_params.compression_enable) { > + if (crtc_state->dsc.compression_enable) { > DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); > return false; > } > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index d4fb7f16f9f6..f41a9336476b 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -323,7 +323,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > struct intel_crtc_state *pipe_config) > { > struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; > - u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; > + u16 compressed_bpp = pipe_config->dsc.compressed_bpp; > u8 i = 0; > int row_index = 0; > int column_index = 0; > @@ -332,7 +332,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, > vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; > vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; > vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > - > pipe_config->dsc_params.slice_count); > + pipe_config->dsc.slice_count); > /* > * Slice Height of 8 works for all currently available panels. So start > * with that if pic_height is an integral multiple of 8. > @@ -491,7 +491,7 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > u32 pps_val = 0; > u32 rc_buf_thresh_dword[4]; > u32 rc_range_params_dword[8]; > - u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; > + u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; > int i = 0; > > /* Populate PICTURE_PARAMETER_SET_0 registers */ > @@ -514,11 +514,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), > pps_val); > } > @@ -533,11 +533,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), > pps_val); > } > @@ -553,11 +553,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), > pps_val); > } > @@ -573,11 +573,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), > pps_val); > } > @@ -593,11 +593,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), > pps_val); > } > @@ -613,11 +613,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), > pps_val); > } > @@ -635,11 +635,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), > pps_val); > } > @@ -655,11 +655,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), > pps_val); > } > @@ -675,11 +675,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), > pps_val); > } > @@ -695,11 +695,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), > pps_val); > } > @@ -717,11 +717,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), > pps_val); > } > @@ -740,11 +740,11 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > * If 2 VDSC instances are needed, configure PPS for second > * VDSC > */ > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); > } else { > I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); > - if (crtc_state->dsc_params.dsc_split) > + if (crtc_state->dsc.dsc_split) > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), > pps_val); > } > @@ -763,7 +763,7 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); > I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); > I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(DSCC_RC_BUF_THRESH_0, > rc_buf_thresh_dword[0]); > I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, > @@ -782,7 +782,7 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > rc_buf_thresh_dword[2]); > I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), > rc_buf_thresh_dword[3]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), > rc_buf_thresh_dword[0]); > I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), > @@ -824,7 +824,7 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > rc_range_params_dword[6]); > I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, > rc_range_params_dword[7]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, > rc_range_params_dword[0]); > I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, > @@ -859,7 +859,7 @@ static void intel_configure_pps_for_dsc_encoder(struct > intel_encoder *encoder, > rc_range_params_dword[6]); > I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), > rc_range_params_dword[7]); > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), > rc_range_params_dword[0]); > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), > @@ -909,7 +909,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > u32 dss_ctl1_val = 0; > u32 dss_ctl2_val = 0; > > - if (!crtc_state->dsc_params.compression_enable) > + if (!crtc_state->dsc.compression_enable) > return; > > /* Enable Power wells for VDSC/joining */ > @@ -928,7 +928,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); > } > dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; > - if (crtc_state->dsc_params.dsc_split) { > + if (crtc_state->dsc.dsc_split) { > dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; > dss_ctl1_val |= JOINER_ENABLE; > } > @@ -944,7 +944,7 @@ void intel_dsc_disable(const struct intel_crtc_state > *old_crtc_state) > i915_reg_t dss_ctl1_reg, dss_ctl2_reg; > u32 dss_ctl1_val = 0, dss_ctl2_val = 0; > > - if (!old_crtc_state->dsc_params.compression_enable) > + if (!old_crtc_state->dsc.compression_enable) > return; > > if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index ada57eee914a..50f2a392f00e 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4566,7 +4566,7 @@ static int i915_dsc_fec_support_show(struct seq_file > *m, void *data) > intel_dp = > enc_to_intel_dp(&intel_attached_encoder(connector)->base); > crtc_state = to_intel_crtc_state(crtc->state); > seq_printf(m, "DSC_Enabled: %s\n", > - yesno(crtc_state->dsc_params.compression_enable)); > + yesno(crtc_state->dsc.compression_enable)); > seq_printf(m, "DSC_Sink_Support: %s\n", > yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); > seq_printf(m, "Force_DSC_Enable: %s\n", > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
